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Mass Production of 450mm Wafers Bumped Back Again: 2018 67

Taco Cowboy writes with news on the slipping schedules in the move toward both larger wafers and 3D integrated circuits in the semiconductor fab world. From the articles: "TSMC ... said it planned to start mass-producing next-generation 450mm wafers using advanced 10-nanometer technology in 2018. The advanced 10-nanometer chips could first be used in mobile devices and other consumer electronics, like game consoles, that demand high-performance and low power consumption. The plan was included in the latest technology roadmap unveiled by TSMC about one year after the chipmaker attributed its delay in making 450mm wafers, originally scheduled in 2015, to semiconductor equipment suppliers' postponement in developing advanced equipment for manufacturing amid the industrial slump. Chipmakers can get 2.5 times more chips from a 450mm wafer than from a 300mm wafer ... The industry's gradual migration toward 3D ICs with through-silicon vias (TSV) is unlikely to happen until 2015 or 2016, according to sources at semiconductor companies. Volume production of 3D ICs was previously estimated to take place in 2014. Leading foundries and backend assembly and test service companies have all devoted much of their R&D efforts to TSV development, and are making progress. The major players are believed to be capable of supporting 3D ICs by 2014, but the emerging technology going into commercial production may not take place until around the 2015-16 timeframe." Probably one of the most interesting presentations at HOPE9, "Indistinguishable From Magic: Manufacturing Modern Computer Chips," covered modern semiconductor fabrication and why these things are cool. If you're interested in more background (what do all of those TLAs mean?), check out the slides / audio (or attached video of the presentation from YouTube).

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Mass Production of 450mm Wafers Bumped Back Again: 2018

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  • by hankwang ( 413283 ) on Wednesday September 05, 2012 @01:23PM (#41236725) Homepage

    450mm means that you end up with fewer incomplete chips on the edges of your wafer,

    A standard die is 26x33 mm, which is much larger than the vast majority of the chips; most dies already contain multiple chips. Therefore, the edge loss is not as big a deal as you would think.

    What is more of a cost saver is that most of the processing steps (applying photo resist, developing the resist, etching, ion implantation, annealing, and so on) are relatively easy to scale up to larger wafers, thereby reducing the process costs per unit of wafer area.

    A big exception here is the lithography process, which gets significantly harder for bigger wafers, since it involves rapidly moving a wafer around with nanometer accuracy. A bigger wafer requires a bigger, stiffer, and therefore heavier wafer stage. ASML manufactures lithography tools that can do up to 175 wafers per hour [] (300 mm diameter) per hour, with an accuracy ("overlay") of 5.5 nm; that is about 3 dies per second. To give an idea of the scale: imagine that a vehicle is moving at 100 km/h, making multiple sharp turns per second, and tracks the ideal trajectory within 500 nm. And then the customer says: nice that you can do that with a sports car, but it's too small; can you build a heavy SUV that can do the same thing? (So there, a car analogy)

    This is why Intel, TSMC, and Samsung have invested into ASML to speed up the development of 450 mm litho tools.

    Disclosure: I work for ASML, but the above opinions are my own.

  • by CaptBubba ( 696284 ) on Wednesday September 05, 2012 @01:42PM (#41237021)

    The lithography is one aspect but what about the deposition/etching equipment? It is spread across multiple vendors and getting them all to support 450mm is going to be one heck of a challenge when for the most part they have only just gotten 300mm production perfected. The chip manufacturers won't/can't settle for 450mm tools that don't hit or exceed the quality of work produced by current 300mm tools because the process nodes now depend on that quality to produce working chips. Maintaining anisotropic plasma etch selectivity or deposition thickness uniformity on over double the area without resorting to much slower processing is going to be a really tough target to hit.

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