Want to read Slashdot from your mobile device? Point it at m.slashdot.org and keep reading!

 


Forgot your password?
Close
typodupeerror
×
Hardware

TSMC To Spend $10B Building Factory for 450mm Wafers 104

Posted by Soulskill from the those-are-some-small-cookies dept.
An anonymous reader writes "With demand for processors growing and costs rising, using larger wafers for manufacturing is highly desirable, but a very expensive transition to make. TSMC just announced it has received approval from the Taiwan government to build a new factory for 450mm wafers, with the total cost of the project expected to be between $8-10 billion. The move to larger wafers isn't without its risks, though. Building new facilities to handle production is the easy part. The industry as a whole has to overcome some major technical hurdles before 450mm becomes a viable replacement for the tried and tested 300mm process. TSMC's chairman Morris Chang has stated the next five years will be filled with technical challenges, suggesting 450mm wafers may not be viable until at least 2017."
This discussion has been archived. No new comments can be posted.

TSMC To Spend $10B Building Factory for 450mm Wafers More

TSMC To Spend $10B Building Factory for 450mm Wafers

Comments Filter:

  • How about (Score:4, Informative)

    by afidel ( 530433 ) on Tuesday June 12, 2012 @04:36PM (#40300523)
    How about they focus on fixing their 28nm production problems before they set their eyes on lowering cost through bigger wafers. It's not like many of their most lucrative clients aren't hobbled at the moment by lack of supply for their top bin parts. Oh, yes they are.

    • How about they focus on fixing their 28nm production problems before they set their eyes on lowering cost through bigger wafers. It's not like many of their most lucrative clients aren't hobbled at the moment by lack of supply for their top bin parts. Oh, yes they are.

      Apply for the CEO's job then.

    • Re: (Score:2)

      by Jeng ( 926980 )

      How about they build for tomorrow so they aren't stuck with yesterdays technology?

      They can build new factories that will use new technologies at the same time that they are operating present factories working on perfecting current technologies. It is not a one or the other situation, it is best to do both.

      • Re: (Score:2)

        by afidel ( 530433 )
        True, but I doubt there are that many good process engineers in the world and the ones TSMC employs really, really need to be focused on fixing their current process, not working on setting up the new factory (though I guess site prep probably takes a year or more so it's admittedly probably not an issue). I'm just personally annoyed that I'm still running a 3 year old GPU because the inexpensive low power parts aren't available because 100% of current production is going to the highest margin parts. I want

      • Re:How about (Score:5, Interesting)

        by Penguinisto ( 415985 ) on Tuesday June 12, 2012 @05:18PM (#40301037) Journal

        Small prob with that...

        Intel recently built up (still building? can't recall) a new fab here in Oregon. It'll cost them $1bn or so, all said and done. Dropping that many ducats at a time gets expensive after awhile, even for a beast as big as Intel. Meanwhile, they still have a fab going that was originally built in the 1980's (the Aloha facility, if you're curious), and after they're done running whatever iteration they have passing through it now, it'll be useless as a fab (the walls are basically swiss cheese by now with all the holes punched and patched through them to accommodate new processes, new chip types, new machinery, etc).

        Personally, I'm kind of curious how a 450mm wafer is going to do them much good.

        Having worked in the solar industry (growing crystal is the same process as semiconductors for mono PV wafers), the CZ process [wikipedia.org] used to grow monocrystal wafers eats a lot of time, and you can only get so much weight hanging off the "seed" (starter crystal) before it breaks. There's also the fact that as diameter increases, the need for more precise control over rotational speed during the grow increases (the thing spins at a precise speed, slowly pulling the cylindrical crystal out of a molten vat). I guess what I'm getting at is, sure they can have something at 450mm with enough precision and effort, but the resulting crystal would also have to be shorter overall, if only to keep the weight from snapping the seed crystal (causing the thing to splash back into the vat, tearing the crucible up, making a mess, and oh yeah - ruining the multi-hour run).

        Long story short, they can likely (with a lot of effort, not to mention newer/bigger machinery) get bigger-diameter crystals, but because the seed can only be so big, the wafer yield will likely drop significantly.

        • Re:How about (Score:4, Funny)

          by ibsteve2u ( 1184603 ) on Tuesday June 12, 2012 @05:25PM (#40301161)

          but the resulting crystal would also have to be shorter overall, if only to keep the weight from snapping the seed crystal (causing the thing to splash back into the vat, tearing the crucible up, making a mess, and oh yeah - ruining the multi-hour run)

          No problem; Taiwan small island, less gravity. Care to invest?

        • Re: (Score:1)

          by Anonymous Coward

          You've explained why it's currently not being done. But I think it's safe to assume that TSMC knows all of this, and they obviously think they've found some viable solutions to the challenges you list. If so they gain a competitive advantage. The world is full of things that were at one point considered impossible/impractical/uneconomical. Proving otherwise is how tech advances.

        • Bigger wafers means less waste around the edges where the rectangular chips meet the circular wafer edge. This becomes very important for larger chips such as image sensors. (Not sure if the new process will be used for that, though.) Also, many manufacturing steps are applied to the wafer as a whole, and having wafers with over 2.25 times as many chips makes those steps cheaper on a per-chip basis. Making the boules will be hard, but I think they will find some way of providing extra support for the boule

          • ...Thinner wafers may also get more out of each boule...

            Going to thinner wafers is very difficult as the wafers become more fragile and are also more likely to warp during processing.

            • Sorta.

              They likely use the same wire-saws to carve 'em out that I saw in the solar industry - the biggest worry there is kerfing along the face of the wafer, making it harder to surface properly. Once you start getting too thin, it ain't warping you have to worry about, as much as you have to worry about the damned thing shattering.

              • Yes it rather negates the savings of getting say 10% more wafers out of a boule when you lose maybe 20% more in production. Post diffusion, once a wafer shatters (the usual way fragile manifests itself), you are pretty well limited to manual processing of the larger wafer fragments if that is possible. It is rather embarrasing to admit that you've lost your year's production of one particular IC batch because your one wafer shattered. :)

                It would be nice to see monocrystalline silicon solar panels come dow

          • Bigger wafers means less waste around the edges where the rectangular chips meet the circular wafer edge. This becomes very important for larger chips such as image sensors. (Not sure if the new process will be used for that, though.) Also, many manufacturing steps are applied to the wafer as a whole, and having wafers with over 2.25 times as many chips makes those steps cheaper on a per-chip basis.

            Cheaper per-chip, yes, but if the production volume is too low or the cost per wafer overtakes the benefit of the added area, then it's not financially viable. And it has to subsume the costs of retooling all your chip production itself from 300mm to 450mm. What if wafers that size oxidize too unevenly, or etch unevenly, or fracture during cutting, or distort due to tension imparted at growth? It won't matter if the individual wafer has 2.25 times more usable area if it ends up being 2.5 times more expen

        • The new fabs being built in Oregon and Arizona are being built with the mentality of "300mm today, upgradable to 450mm tomorrow".

    • How about they focus on fixing their 28nm production problems before they set their eyes on lowering cost through bigger wafers.

      A company such as TSMC can very easily do both: plan and build a 450 mm process and fab, and at the same time improve the 28 nm process.

      Besides, foundries such as TSMC work on demand, and the cutting-edge 28 nm processing is not in high demand at the moment.

    • Re:How about (Score:5, Interesting)

      by tlhIngan ( 30335 ) <slashdot.worf@net> on Tuesday June 12, 2012 @05:42PM (#40301413)

      It's not like many of their most lucrative clients aren't hobbled at the moment by lack of supply for their top bin parts. Oh, yes they are.

      Hence the move to 450mm wafers.

      In semiconductor manufacturing, the cost of the wafer is basically the entire cost - around $1000 each. After processing, it's a bit more expensive. From this they cut it all up and package.

      But two important factors are size of the final die, and the yield. The larger the die, the less per wafer you can make so they cost more. The yield has the same thing - the more bad chips per wafer, the more expensive it becomes because the good chips have to pay for the bad. And there's a relation between size and yield - the larger the chip, the greater the chance that it'll be bad as flaws in the silicon or manufacturing are amplified by the die area.

      So a larger wafer means more chips per wafer, which gives you hopefully less cost per chip (the wafer doesn't cost that much more over the number you get).

      Chips get cheaper for two reasons - enhanced yields (as processes get refined) and moving to smaller nodes (each chip consumes less die area and thus you can fit more per wafer).

      For chips that are fixed-area, like say a full-frame dSLR sensor - it can mean cheaper cameras as yields get higher.

      For larger die chips, like the largest FPGAs (which can easily cost $15,000+ each) it can bring down their cost. And memory is die-area-limited, so larger wafers mean they can be bigger as well.

      • Re: (Score:2)

        by Kjella ( 173770 )

        Except this isn't like process improvements where you can make X% more chips using the same material, going from 300mm to 450mm is like cooking a double batch where you still need double the ingredients. There's obviously some advantages in that you get less edge compared to area (50% increase in edge, 125% in area) which means less waste and less edge yields - which are generally lower than in the center, 450mm equipment will cost more but less per die area however it's not revolutionary. Most seem to sugg

    • They're not the only ones building factories for 450mm wafers. Intel is already doing it for one. If they don't keep up with the other players in the market they won't have to worry about 28nm production problems if they have no customers. 450mm is 3x larger than 300mm, that's a pretty big cost saving there.

  • TSMC (Score:1)

    by Anonymous Coward

    Taiwan. Semiconductor. Manufacturing. Company.

  • Our CEO (based in Silicon Valley) makes regular trips to Taiwan. He tells me of massive developments out there, office parks the size of the city of Fremont are springing up left right and centre. Says there's this government organisation (can't recall its name) that takes in graduates as resident interns, carries out pure research, incubates new companies, and is a driving force behind the country's growth.

    Anyone on here from Tawian that can confirm this? Sounds to me like they're kicking ass over there.

    • Re:Taiwan's where it's at (Score:5, Funny)

      by Yvan256 ( 722131 ) on Tuesday June 12, 2012 @05:11PM (#40300949) Homepage Journal

      Sounds to me like they're kicking ass over there.

      It's not like they have a choice. The government outlawed chewing gum.

    • Fab wise? (Score:5, Informative)

      by Sycraft-fu ( 314770 ) on Tuesday June 12, 2012 @06:45PM (#40302233)

      It is big, but then so is the US and more cutting edge research is going on here. Intel is already on the 22nm node, and I don't mean playing with, I mean shipping chips in mass quantities to retailers and OEMs (Ivy Bridge). TSMC is on the 28nm half node currently, with plans to go to the 20nm half node about the time Intel goes to the 14nm half node.

      In terms of 450mm wafers, well Intel is going there too or at least that is the plan. Fab 42 is under construction in Chandler Arizona right now and will be 14nm process, 450mm wafer. It is slated to start commercial production in 2013, and Intel has been pretty damn good about hitting its dates on fabs.

      No doubt Taiwan is big for semiconductor fabrication, as TSMC is one of the biggest fab-for-hire outfits out there. However if you think all the R&D is going on there, all it means is you've not paid attention to Intel. They are ahead of all other processes currently (and usually are) and they upgrade at a fantastic rate. They do real ground breaking research too, and have to as they are usually leading the pack. One cool thing they have in their latest process is multi-gate transistors, which is a first for CPUs as far as I know.

  • going to a new technology for an industry has risks? [YOU DON'T SAY]

  • Fuck Everything (Score:5, Funny)

    by oldhack ( 1037484 ) on Tuesday June 12, 2012 @04:53PM (#40300691)
    We're doing 500mm!
  • Quoth TFS:

    from the those-are-some-small-cookies dept

    A ~18" cookie [google.com] is small to you? Did /. outsource to Brobdingnag [google.com] ?

  • can someone explain to me why every generation, like changing from 45nm to 32nm lithography or changing wafer size from 300mm to 450mm or whatever takes building a brand new multi-billion dollar fab when you'd think they'd build the machinery and everything that goes along with it to um, 'scale' to some extent? Certainly there must be machines in these fabs that can be re-programmed to handle changing requirements.

    • Re: (Score:3, Interesting)

      by MarioMax ( 907837 )

      Being that I work in Intel's Fab 32, I can speak on authority on this.

      Smaller lithography means you need much better process control and tighter control limits. Machines that can produce quality die for a 45nm lithography might not get the job done at 32nm, and machines that work at 32nm lithography might not work for 22nm, at least not without some serious upgrades to your existing machines, process controls, etc. It is not a trivial task to perform a die shrink, even without architecture changes.

      Also chan

      • Hey Mario, maybe you can enlighten me and the rest of us here.

        How labor intensive is silicon fabs? I had thought it was capital-intensive rather than labor-intensive and yet so many fabs are off-shored. Is it the water consumption/the enviro regulations?

    • Because all of the tools improve over time. The next generation plasma etching system will provide cleaner, more consistent etches. The next generation metal deposition systems deposit more quickly and more uniformly. As we move process generations, the tolerances and requirements on all these other processes also increases, and better processing is required to support a smaller process and result in good yields.

      • Also I should add, a fab is a considerable investment, they create chips for more than one process generation. Thus when it's time to update the fab to a newer process generation, all the tools are essentially ancient. For example, Intel has older 65 nm fabs running (obviously not producing i7s but for other items such as system controllers).

      • Especially when you're trying to move to a 14mn process. The silicon atoms are only 0.2nm wide...When you're building cmos structures and your transistors are supposed to have 5 silicon atoms per gate and one has 6 and the other has 4 that's a huge variation that could ruin your whole chip.

  • . . .is that it's cut from a single silicon crystal (called a boule [wikipedia.org]), two meters long, weighing several hundred kilos, with a defect density so low that it is commercially useable to make chips 25 mm on a side, 0.5 mm thick, with 20 nm feature size.

  • "Intel Corp., Samsung Electronics and TSMC today announced they have reached agreement on the need for industry-wide collaboration to target a transition to larger, 450mm-sized wafers starting in 2012." -- 6 May 2008 [phys.org].

  • My estimates put the Die's per Wafer at:
    300mm = 58615762400 DPW
    450mm = 10228963043666936 DPW
    If the newest 22nm process is used. By the time the factory gets up and running there may be even better efficiencies that could be adapted. It is an expensive venture but at some point either the economics work out or you need to build a new factory anyways. It is good to see progress.
    • Please check your calculations again. You're so far off that you must not be thinking right.

    • My estimates put the Die's per Wafer at:
      300mm = 58615762400 DPW

      Show your work! :)

      (300/2)^2*pi/160 [wikipedia.org]=442 [google.com] and that's assuming no room for cutting/packaging/waste.

    • Re: (Score:1)

      by Anonymous Coward

      Disclaimer: working in the industry.

      Die per wafer on 300mm wafer: 50 to 500, depending on the product...
      I don't even want to know how you get those numbers

Slashdot Top Deals

Our OS who art in CPU, UNIX be thy name. Thy programs run, thy syscalls done, In kernel as it is in user!

Close