Cheaper, More Powerful Alternative To FPGAs 108
holy_calamity writes "Technology Review takes a look at a competitor to FPGAs claimed to be significantly faster and cheaper. Startup Tabula recently picked up another $108m in funding and says their chips make it economic to ship products with reconfigurable hardware, enabling novel upgrade strategies that include hardware as well as software."
Re:Me like (Score:4, Interesting)
For sure. Don't worry about getting the hardware working exactly right, we'll ship it now and release an upgrade later.
FPGA for designing ASICs, or small-volume chips (Score:3)
If you're designing an ASIC, one traditional method is to do your design, flash it to FPGA, test it, debug, repeat, and when you're done, send it out to the fab to get it burned into ASIC. So yes, it's hardware upgrades through programmable circuitry, and you might be doing multiple upgrades per day.
If you're doing small production runs of chips, for instance for custom hardware, you may want something that's fast but you're not going to make 10,000 of them so you don't want to pay the price of burning ASI
ASICs got more expensive! (Score:3)
ASICs actually got more expensive. The individual ASIC is cheaper now, but the non recurring costs of making a ASIC went up a lot. Smaller process nodes need more masks and more complicated masks.
If your mask set is $2.000.000 and you are going to sell ASICs 10,000 made with it, even if the individual ASIC is free after paying for the masks, you are still at $200 per piece. The $100 FPGA is a better option then and at 10.000 pcs you are going to get a pretty large fpga for $100.
Re:ASICs got more expensive! (Score:4, Informative)
ASICs actually got more expensive. The individual ASIC is cheaper now, but the non recurring costs of making a ASIC went up a lot. Smaller process nodes need more masks and more complicated masks.
If your mask set is $2.000.000 and you are going to sell ASICs 10,000 made with it, even if the individual ASIC is free after paying for the masks, you are still at $200 per piece. The $100 FPGA is a better option then and at 10.000 pcs you are going to get a pretty large fpga for $100.
Sure. But the older processes are still available. I haven't looked at pricing for a few years, but IIRC last time I digged into this, $2M was about the right price for preparing masks for 65nm processes. However, if you went for something a few process steps older (e.g. 0.35 or 0.5 micron processes which are still readily available), you'd be looking at somewhere in the region of a hundredth that price. And a 0.35um CMOS ASIC can perform similarly to a 65nm FPGA: on both you'd expect non-trivial designs to operate with clock frequencies in the region of low hundreds of MHz.
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If you care only about logic of the FPGA that might work, but the FPGA isn't just logic but also IO cells, SERDES, builtin memory controllers, ram resources etc.
Because of that you can't replace the FPGA with a ASIC manufactured in a many generations older process, two or three process nodes is fine and you can use a gate array process to lower the mask cost.
But that doesn't fundamentally change the problem: For low volume products FPGAs are cheaper than ASICs. These days you need a pretty big volume to mak
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Add to that, security becomes a real nightmare, when you can no longer trust you hardware.
Seems pointless to replace the CPU with a programmable chip but certainly putting the OS onto a programmable chip seems like a worthwhile exercise, certainly ramp up boot times and drive compact OS's.
Re:putting the OS onto a programmable chip (Score:2)
Isn't that what SSDs are for?
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From a SSD it still has to be loaded up and put into active memory, with a programmable cpu it could already be there and ready to go, the second power on is achieved. Plus there is the possibility of performance gain with a parallel processor OS.
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I think the biggest flaw is that manufacturers don't necessarily want to update your existing device -- they want you to buy a new one. So whether the technology exists affordably really doesn't matter.
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(Even without reconfigurable hardware, it is hardly out of the ordinary among 'enterprise appliance' type hardware to pay nontrivial money for unlock codes that let you use parts of the
Re:Me like (Score:5, Informative)
Here's the thing people don't seem to realize: FPGAs *are* cheap.
Case in point: Xilinx XC3S50A. $5.75 at Avnet. Comes in a hobby-solderable VQFP and you can make it work on a 2-layer board. Add a SPI flash to boot from (or a nearby micro with ~50K of spare flash), an oscillator, and +3.3V/1.2V regulators for power and you're still under 10 bucks parts cost - in low quantity.
This chip is only bottom of the line, but it's full of awesome stuff - "DCM" clock multipliers that can let you run FPGA designs at 250+ MHz by multiplying up slow external clocks, three 18x18 multipliers that run at almost the same speed, three 2Kbyte SRAM blocks that you can use as instruction/data memory for processors (eg, a Picoblaze, which can run at 100+ MHz).
These are great little things to play with as a hobbyist. I've contemplated making an Arduino shield with a small, cheap FPGA for people to experiment with, but I never really could figure out any good way to get data and signals in and out of the chip in a way that shows off what FPGAs are really good at.
Comment removed (Score:4, Interesting)
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DSPs (good for audio processing, among other things) can be (and often are) implemented in FPGAs, however I assume you'd need a 16 or 24-bit implementation for high-quality audio.
I don't know how much an FPGA capable of that would cost, but there's lots of info online so it must be reasonably affordable.
http://www.google.com/search?q=fpga+dsp+audio [google.com]
They are (Score:2)
Here's the thing people don't seem to realize: FPGAs *are* cheap.
They are. I do embedded design for a living. And I'm yet to see a design cross my desk that doesn't have a Xilinx or Altera chip on it. You see them typically used as glue logic, like buffers in between the cpu and pcmcia slot. Or clock generation. Discrete components for that would be *far* more expensive.
FPGAs are already a bargain. Sure, if something cheaper and faster comes along that'll be great. But not really necessary.
Re:Me like (Running FPGA Examples) (Score:2)
http://papilio.cc/ [papilio.cc] Home of the Papilio FPGA board, which has a similar intent to the Arduino. It currently supports a stack CPU and an AVR emulating CPU. The AVR CPU supports the Arduino tool chain. Here is another site for projects with this board. http://gadgetforge.gadgetfactory.net/gf/ [gadgetfactory.net]. You can get it for $US 50 or 75, depending on the FPGA size.
The Gameduino http://excamera.com/sphinx/gameduino/ [excamera.com] is an Arduino shield with an FPGA that suppo
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"Xilinx XC3S50A" : of course, that's the very low-end line-of-product from Xilinx. Additionally, Spartan 3 is an old generation.
On the other hand, check the price of large, high-speed FPGA from Xilinx's Virtex 6 family : nothing below $1000. Top at $10000.
Ouch.
http://avnetexpress.avnet.com/store/em/EMController/Programmable-Logic/FPGA/_/N-4294649145%204294609580%20100235?Nn=25&action=products&cat=1&catalogId=500201&cutTape=&inStock=&langId=-1&myCatalog=&proto=®ionalSto [avnet.com]
FPGA is nice but not a magic bullet. (Score:1)
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It can't grow bluetooth, or gps, yet.
it can become the receiver for either though. which means all you really need to do is to setup multiple antenna's that can be lengthened/shortened as needed.
Now there's an experiment that needs more research. how do design an "modular" antenna so that you can change which frequencies are received/transmitted allowing for a truly broad spectrum operations.
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It can't grow bluetooth, or gps, yet.
Well, there are devices that can, which are basically just slightly "better" PSoCs .
That's not the point. It doesn't seem like FPGA/PSoCs could ever be as cheap as a dedicated solution. Even if there is a breakthrough in fab that makes FPGAs closer to their dedicated counterparts, those efficiencies should also apply to the dedicated process.
Basically, FPGAs and PSoC always involve some extra overhead for the flexibility. The overhead may diminish more and more, but as things scale up those small overheads
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No, you're not doing any funky RF on-chip, unless someone is making specialized FPGAs with the RF goodies baked-in.
FPGAs are wizard for dev cycles, though, if your changes are only in the logical realm. No need to turn new boards; just reprogram the FPGA and get on with your life.
This guy's real problem is it's going to be as little as 1/N as fast as the N times bigger circuit he's replacing.
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Welcome to 2011
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i've been turning down jobs in software-defined radio since...jeebus...1999?
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The FPGAs needed to replace even fairly lousy shipping discrete GPUs cost on the order of $10k each. To replace a decent middle-of-the-pack GPU with an FPGA, you'd need to spend on the order of $100k in chips just for one board. Never mind that the board would consume on the order of 1kW of power, and good luck if your board assembly house messes something up: you lose a house's worth of hardware. It'd probably cost a couple $k to get the board assembled!
Delay Lines (Score:2)
Mmmm.... 40+ years after going out of style as "Hopelessly Obsolete", Delay Lines return to the cutting edge.
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Erm, no. This is kind of the opposite of delay lines. It's more like a pipeline, where each segment of the pipe is actually the same piece of silicon real-estate.
Your data goes through the entire pipeline, getting munged just as a pipeline would at each step, and comes out just how you want it.
Problem is, with a pipeline I can have a different datum in each segment. With this, one datum has to go through all the steps before I can feed another datum into the pipeline.
The pipeline gives me an N:1 speedup
FPGA for shipping products? (Score:1)
I've got kicked out of school with an EE degree, gone into software business (yeah, I know), and never looked back.
Do they ship products, other than dev kits, with FPGA?
Re:FPGA for shipping products? (Score:5, Informative)
Yup. Especially write-once FPGAs.
Sometimes making an FPGA is cheaper than building an equivalent board. You can get preprogrammed cells for entire microprocessors now. And lots of other library cells. Build an entire custom computer into a single package, if you want.
It's not dirt-cheap, but it's easy, and saves an assload on inventory.
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I didn't know write-once FPGAs were much popular
Most products I've seen use either a serial EEPROM, flash or code (up)loaded from another processor on the board.
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They're not... as on most things blair1q is an idiot.
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In other words, you might want to stick your nose in some medical equipment before you judge the popularity of FPGA's...
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Sure, but only some market segments.
For example, FPGAs are never as power or area efficient as dedicated silicon gates, and area equates to manufacturing cost. This tends to mean that for volume consumer apps, a dedicated ASIC will win out in the end.
The flip side is that FPGAs are much quicker and cheaper to develop for than an ASIC, so for specialist applications or small markets, FPGA win out.
These days FPGAs are starting to include more and more hardened blocks such PCIe interfaces, flash controllers a
Re:FPGA for shipping products? (Score:4, Informative)
All of our product have some sort of reprogrammable logic. PLD , GAL , EPLD, CPLD , FPGA, and some the designers should have been shot for making.
Without it we would not be able to design a product and get it to market with any hope of turning a profit. It keeps engineering costs low allows us to make changes for regulatory requirements and allows end users to load new firmware and fix problems in the field.
Some of our products are niche and low volume and some of our products are very high volume and we're growing.
Re:FPGA for shipping products? (Score:4, Interesting)
I've got kicked out of school with an EE degree, gone into software business (yeah, I know), and never looked back.
Do they ship products, other than dev kits, with FPGA?
All the time. They tend to be low volume items with high unit cost. Cisco has been a big consumer FPGAs forever. It's not even all that uncommon to find FPGA's in consumer electronics, though they tend to be very small parts used a glue logic.
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Many IO cards use FPGAs.
I have seen them in interferometer controllers, motor servo boards, fast multi-io cards, etc. Most of the stuff is low quantity, expensive stuff ($5000+ per item), so it seems like its easier to put in an FPGA than creating a new chip for a few 100/1000 copies...
Re:FPGA for shipping products? (Score:4, Informative)
Plenty of tools like oscilloscopes now use FPGA's. Low end FPGA's are a couple of dollars tops, which is cheaper then the purchase plus production costs for a bunch of discrete chips.
A lot of hobbyist producers make designs with those low end FPGA's because it can be cheaper to use one FPGA over a whole bunch of products rather then stocking equivalent discrete IC's (ie you can buy an FPGA in 1000 quantities and use it across 10 products).
Of course this new product is just a cheaper FPGA, and their marketing claims are bullshit. Consumer electronics producers do not want upgradeable or repairable electronics. They want to be in the "fashion" business like Apple and sell new "upgrades" every year.
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Lots of dedicated video encoder/compressor boxes on the market, I haven't seen one yet that wasn't FPGA based.
midi synth (Score:2)
Functional Programming will love this (Score:1)
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You can do that with FPGAs, just go through a defunctionalization step which spits out a FSM. See Bill Harrison's work at U. of Missouri.
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They may be attacking the wrong castle (Score:3, Interesting)
The real problem with FPGAs is the painfully byzantine tools you have to use to deal with them. The chips themselves are fine.
There is a lot of room for disruption in the programmable logic tools industry. If this company is smart, they will focus on workflow and toolchain innovations, rather than becoming too distracted by shiny silicon baubles. Shorten the edit-simulate-synthesize-test cycle and you will make a lot of people happy.
Then again, you should never argue with a man who buys his ink by the gallon, or his wafers by the acre.
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http://www.ni.com/fpga/ [ni.com]
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Oh god no.
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Then again, you should never argue with a man who buys his ink by the gallon, or his wafers by the acre.
Especially when he's so incredibly wrong. Silicon costs more like $10 million per acre right now (I had to look up the conversion, it's a kinda weird unit). The reason FPGAs are expensive is because of all the crap you need to implant and deposit and remove in order to make that silicon into a chip. And then you have the added cost of testing every single transistor in the chip to make sure that no little dust particle floated by and ruined the chip. That's where the size really hurts you, because one t
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I think it's closer to $100 million per acre, not $10 million, but what do I know? (That's based on ~$8000 per 12-inch wafer, which is an estimate I saw a year or two ago. Of course, maybe this guy is only getting 10% yield, in which case he's essentially right - and there's plenty of chips that are that bad, at least early in the product and process lifetime...)
NeoCad + DIY FPGA (Score:4, Interesting)
The disruption you mention almost happened in the early 90's. NeoCAD [findarticles.com] produced a compete competing tool chain for Xilinx FPGAs, including the place and route, for the then state-of-the-art 4000 series. Their software was better than Xilinx's, including things like a graphical layout editor. Xilinx was having none of it and bought NeoCAD. Quite a few NeoCAD features made it into the Xilinx software, eventually. Soon after that Xlininx started publishing less information on their FPGA's interconnect networks, and there has never been another attempt at writing such software.
Personally, I think writing a clone of the Xilinx software, today, is the wrong thing to do. It would be less effort to design and manufacture an "open source" FPGA, and write the necessary software from scratch, than to reverse engineer Xilinx's place and route.
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I have been thinking about the same thing as of lately. Creating an open source FPGA with full tools: Synthesis, Place and Route, low level FPGA editor and more.
I was thinking as a start to make something similar to the old Spartan-1 type fpga in a newer process. The marked targeted would be in between the CPLD and the smallish fpga's. (100 luts to 1000 luts)
The reason for this is that CPLD's are simple to integrate on board (no non volatile storage, only one supply voltage) but for small fpga's you already
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Checkout: http://www.maxeler.com/ [maxeler.com]
They've been getting some pretty crazy results. If i understand correctly, they've got a completely innovative workflow, tool-chain and abstraction. I think they've even created their own simulation tools that give you cycle-accurate results 1000x faster than modelsim.
I'll believe it when I see it (Score:2)
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what happens if clock skew carries signals across folds?
I assumed that data was registered between fold switches.
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No, they had to do their own synthesis since the synthesis step has to be combined with the time domain place/route to work. This is one of the reasons they have burned through so much money. We've not been able to establish a single application that the Tabula technology improves. This is all smoke and mirrors.
And there are no FF's in the technology -- only latches. We have no idea how clock domain crossing is accomplished.
Transputer on a Chip?... (Score:1)
To me, after reading the papers, it looks like they reinvented (or reimplemented) Transputer architecture, but in a single chip, and with a different API.
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To me, after reading the papers, it looks like they reinvented (or reimplemented) Transputer architecture, but in a single chip, and with a different API.
Uh, no. I'm sorry, but you probably have no clue what FPGAs are if you think that. Possibly transputers too.
There is no "API". FPGAs aren't devices for executing software. They're giant arrays of lookup tables used to implement logic functions. If you have a 16-entry LUT indexed by 4 bits, you can program the LUT to implement any possible logic function on 4 input bits. If you've ever taken a digital logic course, they're nothing more than truth tables. These LUTs and a bunch of other hardware buildi
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Transputers were general purpose CPUs designed to be tied together in some kind of network (I don't recall the details). They looked nothing like FPGAs, and didn't do this kind of time-sliced trick.
I seem to recall that one of the contemporary transputer-like designs used "CPUs" not much more intelligent than a LUT, though...
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Because it's scary when something costs ONE...BILLION...DOLLARS!!!
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Because 99% of people buying computers would find that a huge hassle?
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Because FPGAs are very expensive. The top end ones cost more than people want to spend on their entire desktop, just for that one chip. Custom logic will always be cheaper, because it only gives you what you need.
Also, your idea of shutting it down to save power doesn't really help. All chips go to sleep when not in use, there's nothing special about FPGAs in that respect.
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I think it's mostly a matter of the toolchain being different and very, very primitive. My impression of Verilog (from a few trivial experiments) is that it's the sort of language you might expect someone to design 40 years ago. Also, many idiom are different. Some things may be easier, but programmers tend to take for granted that they can make random memory accesses -- they don't expect to need to implement a memory controller to do so.
Amazing use of factors (Score:4, Funny)
Teig estimates that the footprint of a Tabula chip is less than a third of an equivalent FPGA, making it five times cheaper to make, while providing more than double the density of logic and roughly four times the performance.
That is 6X more impressive than any other use of factors in a sentence... ever.
steve teig's latest failwin (Score:5, Interesting)
the guy behind Tabula is behind a number of "failwins" in the electronics industry - a fail in that the technology ended up being pointless and rejected by the market, but wins in that his companies were all bought out by suckers for quite a bit of $$$$
two examples:
- X initiative (use 45 degree routing on chips) - look at http://www.xinitiative.org now - 100% dead. look at it, and all the wonderful claims he (and his sucker followers) made in archive.org.
- Simplex solutions - built a large number of poor quality EDA tools (poor because they never got adopted and so never got the real bugs worked out and features required for real work) but looked very shiny, so were sold to cadence for a fairly large sum of money (relative to the low dev. cost). All but one of the simplex tools (now called cadence QRC) has been EOLd by cadence, and QRC will be thrown out just as soon as anyone cares enough to replace it with something better.
You can bet Tabula, if it succeeds at all, will be another failwin. It will be bought by one of Xilinx or Altera (the current FPGA duopoly), a couple of minor good ideas will be incorporated into future products and the overwhelming majority of the Tabula technology will be promptly forgotten. ...why? I hear you ask?
The reason is simple: Steve Teig has realized that "spamming" technology really does work (for him) - he has figured out that he can leave it up to much larger corporations to figure out, in their own sweet time, why 99% of his ideas sound great but are actually pointless, in the months and years after they are fooled into acquiring his techno-spam through an acquisition.
From one of his many online bios [c-eda.org]:
He holds over 220 patents. In 2002, he broke Thomas Edison’s record for the number of patents filed by an individual in a single year.
Enough said.
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You point at the 'large number of poor quality EDA tools' in Simplex (which I never used), but you certainly know that EVERY EDA tools (from Synopsys/Mentor/Cadence) have its LARGE set of bugs. Why? Because quality is driven by ASIC design companies, and those companies do not understand that putting pressure on tool prices is hurting overall quality. Anyway.
"in 1982, he invented compiled-
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Wow thanks for bringing my attention to such an interesting and fascinating guy. From what you write he sounds like a truly brilliant engineer and businessman man. Of course only a tiny proportion of all products make the dominating and long lasting impact on the market that you seem to want, think the light bulb, printing press or the integrated circuit. However an even tinier amount of inventions ever make it to the market or generate any revenue at all! This guy has been able to do that over and over aga
Better writeup (Score:4, Informative)
Anyone else remember Starbridge? (Score:2)
I remember Starbridge [slashdot.org], and their audacious claims, and this company sounds like it's trying to accomplish something similar, but aren't being as audacious with their claims.
I do look forward to software reconfigurable hardware, but that does mean it brings a whole new meaning to the word "bricking."
It's basically the same as any other FPGA (Score:5, Informative)
...but it has fast context switching built-in. And you can't control when the contexts switch, they always go in order (as they should, since they're all statically assigned, and are different parts of a single problem, rather than separate problems).
For those that don't know how FPGAs work, here's a basic crash course: they have lots of blocks, each one has a look-up table (say a 4-LUT; 4 inputs, 1 output). The LUT is basically a "read-only" RAM with 4 address bits (so 16 addressable locations), and one data bit. The RAM can be rewritten (this is what is done when they program an FPGA), but it's fairly slow. Tabula changes it up a bit so that each addressable location is 8 bits instead of 1 bit. Since transistors are basically free on an FPGA (they're wire-dominated), this doesn't cost much, and it means that they can time-share pieces of silicon for different purposes without the penalty of reprogramming the chip. Then, each cycle, it'll pick a different one of the 8 bits (though the address, or inputs to the 4-LUT, may be changing at the same time).
It's a fairly straightforward idea, though there's a fair amount of complexity added to the design tools.
However, it's not free. You now have lots of high-speed logic, which is probably using tons of power, and it's switching frequently, which is using tons more power, and even when it's not, it's probably fairly leaky, using even more power. Effectively, you have a 1.6 GHz chip, but to you it seems like it's only running at 200 MHz - but it can do ~8 times more processing per silicon area. You might also think of it as being similar to the Pentium 4 integer units; they ran at twice the clock speed of the rest of the chip, so it seemed like there were twice as many of them (so a single IU could do an add in the first half of a core clock cycle, and a subtract in the second, computing two instructions per cycle).
So this chip is basically trading latency for computing power. The more operations you need to do, the slower it will run, because it'll take more of their folds to implement your logic.
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So it does nothing infinitely fast?
Sounds like a fair tradeoff.
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If Tabula can provide the equivalent of 8 FPGA in a single circuit, it will be a huge win for system designer. Multi-FPGA systems have reduced performance because signals must be propagated between FPGAs, via a limited number of IO pads. A PCB integrating a single FPGA (rather than 8 FPGAs) would be cheaper to produce, more compact, while providing better
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That's not a bad overview, but you need to apply some intelligence to the power consumption figures.
A|G || B|H
-+- || -+-
C|E || D|F
hope you enjoyed the preview (Score:2)
Now back to the original program. Some year fer fools day, /. needs to randomize Preview/Submit.
That's not a bad overview, but you need to apply some intelligence to the power consumption figures.
A|G || B|H
-+- || -+-
C|E || D|F
My first instinct is to set up the eight bit shift register as a pair of four element squares; one clocking on the rising edge, the other on the falling edge. A mux at the bottom selects from the left/right square on alternate cycles.
Your clock is 800MHz instead of 1.6GHz. The time
DSP FPGA (Score:2)
The only FPGA I've used in my own design was a Spartan DSP. Heinlein's magic box isn't going to do you much good implementing 18x18 Wallace trees or adding conventional compute cores.
It's optimized for a very high LUT/pin ratio, in a small, hot package, discounting macro blocks.
I was more enthusiastic about mixed signal ASIC technology [triadsemi.com] from Triad, but on my initial inquiry they haven't lowered the cost of full-custom analog ASICs at the low end. What they seem to offer is a fairly expensive, but far less
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It's optimized for a very high LUT/pin ratio, in a small, hot package, discounting macro blocks.
And that's a very good point. I've seen many, many designs that are far more I/O limited than logic-limited. I actually did a design once that used a very simple, cheap PLD; out of roughly 100 I/O pins, I think we had 4 or 5 unused, but we were only using something like 7% of the available logic. (Granted, we tried to maximize the I/Os that were in use - a couple might not have actually been tied to any logic, but we had them connected so that if we decided we could build logic off of them later, we didn't
I don't know (Score:2)
Power Consumption = Not Ready for Prime Time (Score:2)
"The power consumption if these devices is relatively high, and likely too much for a device like a phone" Dead giveaway that this is a marketing story, not a real proven technological renovation.