'Universal' Memory Aims To Replace Flash/DRAM

siliconbits writes "A single 'universal' memory technology that combines the speed of DRAM with the non-volatility and density of flash memory was recently invented at North Carolina State University, according to researchers. The new memory technology, which uses a double floating-gate field-effect-transistor, should enable computers to power down memories not currently being accessed, drastically cutting the energy consumed by computers of all types, from mobile and desktop computers to server farms and data centers, the researchers say."

But I like volatility!

[melikamp]

Volatility is actually useful for certain security policies: like storing sensitive passwords in computer memory and working with temporarily decrypted files.

Early DRAM

[DCFusor]

though it had a short refresh time spec, would actually hold nearly all the bits for up to a minute, and we made early "digital" cameras out of them, charging up all the bits and letting light discharge the lit up pixels quicker than the others. It was a bit of a bear to figure out the pixel layout -- it wasn't in order, but we did it and even got to two bits or so per pixel resolution by taking more than one shot after a charge, different exposure times. One wonders why someone doesn't just work along those lines. Seems to me for most uses simply increasing the refresh time interval would save tons of power, and also complexity. If you could get it to a couple of days, I'd think that would be fine for most all portable devices, and you'd just use cheap flash as the disk, like now. I am guessing you'd lose some density, as the older, less dense DRAMs had large cells that stored more charge per bit, and that new lower voltage semis are also leakier, but it might be worth looking into anyway. I recall one case where the company I worked for designed some very early disk cache controllers. Well, actually I did about 90% of that. We used DRAM, but simply arranged the code so the basic idling operation (for example, looking for io requests or sorting the cache lookup table) took care of refresh anyway, wasn't too hard at all to manage that, and of course a block read or write always did a full page refresh. Made the thing a little bit faster, as there was never a conflict between refresh and real use in the bargain. This would also be trivial an any current opsys to get done. Probably happens by accident except in real pathological cases.

Interesting

[c0lo]

TFA

"We believe our new memory device will enable power-proportional computing, by allowing memory to be turned off during periods of low use without affecting performance," said Franzon.

Huh! A new chapter opens in the "program/OS optimization" - heap fragmentation will have an impact on the power your computer consumes, even when not swapping (assuming the high density and non-volatility will render HDD obsolete... a "no more swapping, everything is non-volatile-RAM, with constant addressing cost" becomes plausible).

Re:10 Years away

[gmuslera]

I hope that xkcd [xkcd.com] is wrong this time. Would be nice to have most new mobile devices with that in 2 years.

Re:But I like volatility!

[Simon80]

Volatile memory is already vulnerable to reboot attacks, because the data takes a long enough time to rot. Paradoxically, non-volatility could increase security in these cases by making it more obvious that it's not OK to leave sensitive info sitting around in memory.

Re:But I like volatility!

[purpledinoz]

I read somewhere that if you cool DRAM, the data can stay intact for up to 10 minutes. That's plenty of time to remove the modules and extract the data from them. But if this is really a big concern, I wonder if it's practical to zero the memory after a PC is shutdown. Kind of a background routine. Or maybe even short all the lines to drain the stored charges.

Re:Early DRAM

[sxeraverx]

You are correct. Currently, DRAM stores information as a N-channel MOSFET attached to a capacitor. This MOSFET is leaky. There's no getting around this leakage. This leakage acts to discharge the capacitor where the bit is stored.

You can try to decrease this leakage in a number of ways. You can increase the threshold voltage of the gate, but that means you'd have to increase the voltage the DRAM operates at as well, or else you wouldn't be able to charge the capacitor. This means you'd increase the energy-per-operation of the DRAM cell, because you'd have to charge the capacitor up more. You'd burn up more power, because the leakage is proportional to the operating voltage, but the charging energy is proportional to the square of the voltage.

Alternatively, you could increase the capacitance. But this means that the capacitor would take longer to charge, slowing down every operation. Also, doubling the capacitor size means doubling the energy it stores (and therefore burns with every operation). It also makes the DRAM cells bigger, meaning you can't fit as many on a silicon wafer.

Neither of these is what you want to do. In fact, you want to do the opposite for traditional DRAMs. It's counterintuitive, but you get more density, more speed, and less power by increasing the refresh rate (or rather, increasing the refresh rate is a side-effect of all of those). Unfortunately, lithography limits and quantum mechanics mean we're having a hard time going any smaller.

It's truly amazing what we can do. The oxide layer (essentially a layer of quartz glass between metal and silicon) on a MOS these days is 5 atoms thick. We're going to have to come up with something that relies on something other than the traditional semiconductor effects if we want to continue forward.