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Marvell Launches First Triple-Core Hybrid ARM Chip 117

Blacklaw passes along an excerpt from that begins "While other manufacturers are content to develop dual-core ARM processors, Marvell has gone one better — literally — with a new triple-core chip called the Armada 628. The system-on-chip design, based on ARM's v7 MP series, features two dedicated 1.5GHz processing cores plus a third 624MHz core in a single application processor — making Marvell the first company to bring such a beast to market. While two of the cores are a pretty standard SMP setup, as seen in other dual-core ARM implementations, the third is a standalone processor designed for ultra-low-power draw. The idea behind such a design is that when the system is idle, or only running a low-performance application on a single thread, it can shut off the dual-core portion and save oodles of power."
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Marvell Launches First Triple-Core Hybrid ARM Chip

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  • Wait... (Score:4, Interesting)

    by CajunArson ( 465943 ) on Thursday September 23, 2010 @01:10PM (#33677370) Journal

    Why can't it just shut down one of the two normal cores, and run the other core at a highly reduced rate to get the same power savings? Additionally, I've seen plenty of benchmarks where a higher-power draw chip that can get done with a task quickly and drop back to low-power idle mode is actually more energy efficient than a lower-power chip that takes longer to get the task done. What sort of tasks is the third core intended to do that it would be so much more efficient than a regular ARM core?

  • Re:Imagine a (Score:4, Interesting)

    by SimonTheSoundMan ( 1012395 ) on Thursday September 23, 2010 @01:25PM (#33677600) Homepage

    I saw 32, 600MHz ARM chips demonstrated in 1999 in an desktop computer. Check her out: []

  • by Animats ( 122034 ) on Thursday September 23, 2010 @01:30PM (#33677664) Homepage

    There's a tendency to put a little CPU in devices to handle activity when the device is "off". Something has to sit there and watch for the remote if the TV is to be turned on remotely. Many machines have a "wake on LAN" capability, and most servers have an extensive remote management capability built into the network controller. All of these imply some little CPU, invisible to the main operating system, doing things when the device is supposedly "off".

    This isn't necessarily a bad thing, but it does provide an attack surface. Especially since those little machines tend to have very powerful access to the rest of the system, bypassing most security measures.

    This new chip looks like an effort to integrate the "power off" CPU onto the same silicon as the main CPUs. That's a routine use of silicon real estate by putting more on one part. But the concept isn't new.

  • Re:Wait... (Score:3, Interesting)

    by pclminion ( 145572 ) on Thursday September 23, 2010 @01:32PM (#33677694)
    *shrug* -- Even in seemingly low-requirements applications like a laser printer you'll typically find at least two or three microprocessors. It's common for those CPUs to be running at different clock speeds, be closer or farther away from certain kinds of memory, and dedicated to specific tasks. You might have the main core running Linux with a firmware RIP engine while some subsidiary core runs a custom RTOS to drive the print mechanism. This new CPU is just packaging a few of those heterogeneous cores up in a convenient way. In other words, these are the sorts of configurations the industry is using already. I think it sounds interesting, but not really earth shattering.
  • leakage (Score:5, Interesting)

    by YesIAmAScript ( 886271 ) on Thursday September 23, 2010 @01:39PM (#33677788)

    At current processes (44nm, 32nm, etc.), switching power isn't critical at low speeds, it's leakage that is the issue. So a fast (big) processor takes a fair amount of power even if you run it slow.

    Whereas a slow core is smaller, so that means fewer transistors to leak. You also can make the gates out of lower-leakage cells, so that even when on they leak less. This limits top speed which would be a problem for the main core but isn't a problem for this non-main core.

    Having additional low-power cores isn't that strange, many current phone SOCs do this. What is unusual is most of those have one main core and many slower ones and this one has two main cores and one slower one.

  • by Anonymous Coward on Thursday September 23, 2010 @01:48PM (#33677912)

    You have it backwards. The Atom parts are a partial response to ARM and not a cause for it. ARM already ships a large multiple more CPUs than x86 and is starting to eat into the traditional x86 market via smart phones, tablets, set top boxes/appliances, and servers. Intel has responded by producing 'low power' Atoms and running around trying to convince phone manufacturers that 2 hours of battery life would be worth it for 'the full internet experience(flash and legacy windows crap)'. However it's also important to note that Intel is an ARM licensee and could trivially switch to that architecture if they wanted to. However they want to preserve their x86 margins as much as possible rather than becoming a commodity manufacturer.

  • Power != Energy (Score:5, Interesting)

    by Theovon ( 109752 ) on Thursday September 23, 2010 @02:22PM (#33678338)

    It's common for people (myself included) to conflate Energy with Power, but it's often an important distinction. To begin with, technically, we don't consume power. We consume energy (to do work, which is in the same units), and power is the rate at which it is consumed.

    An important factor often left on the floor is processing efficiency, meaning how fast are we getting work done for a given power level. If you reduce power by half, but the work takes twice as long, you've accomplished nothing. For the same amount of work, your battery will drain the same amount. Indeed, what we really want to do here is make systems take less energy, and within reasonable limits, it doesn't matter how much power you consume while you're doing it.

    This has actually been one of the things that makes ARM processors energy-efficient. Not to say they're not also low power, the strategy has always been to build event-driven systems. Something happens (user input, sensor reading, etc.), which causes the CPU to wake up in your embedded system. The ARM processor then blasts through the work to be done, and then goes to sleep, powering down completely until the next event. (Some systems will use intermediate "sleep" states that are less time-expensive to sleep and wake.) An ARM is more efficient than an Atom, in part because it uses less power, but also in part becauses it needs less time to complete the same task.

    In today's technology, this is especially important. At 90nm and 65nm, the Intel Core and Core 2 used clock gating to save power. Functional units (e.g. floating point multiply) that are idle have their clock signals gated, which reduces power being used by that part of the clock distribution tree. This is important because in those technologies, dynamic (switching) power dominates. In the Core i7, Intel uses POWER gating. When a functional unit is idle, it's powered down completely. This is because in 45nm and 32nm CMOS, static (leakage) power is what dominates.

    Going back to ARM, this is something being applied in the Cortex A9. They've made a more complex processor in order to execute out of order, but as a result, computation goes appreciably faster. During computation, leakage is constant. By getting the work done faster and powering down completely, more leakage power is saved. Less time translates into less energy, even if the A9 uses more power than the A8.

  • Re:Wait... (Score:3, Interesting)

    by david.given ( 6740 ) <dg AT cowlark DOT com> on Thursday September 23, 2010 @04:34PM (#33679938) Homepage Journal

    Looks to me like this is designed for the mobile market: two SMP processors to run the application OS, one lower-power processor to run the radio OS. Pretty much every smartphone on the market works like this, albeit with a single application processor.

    The reason is that GSM (and most likely CDMA, although I've no experience of that) is critically real-time and needs a real-time OS to manage: Linux basically doesn't cut it. So you dedicate a complete processor with its own real-time operating system to it. I know that the G1, for example, runs L4/Iguana on its radio processor.

    This allows you to run an ordinary desktop operating system, which isn't hard real time, on the application processor; Linux, Windows, etc.

    There are also legal benefits in that since you can update each OS independently, you don't need to get your device (expensively) recertified by your local radio regulator in order to do an application OS update. If you were using a one-chip device, where there was a single processor that ran both the application layer and the radio stack combined, then you couldn't update one without updating the other.

    This, BTW, is one of the reasons why so many people are interested in virtualisation on embedded devices; if you can run two operating systems at the same time on a single processor, it allows all the benefits of a two-chip device on vastly cheaper single-chip hardware.

Adding manpower to a late software project makes it later. -- F. Brooks, "The Mythical Man-Month"