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IBM Hardware

IBM Unveils Fastest Microprocessor Ever 292

adeelarshad82 writes "IBM revealed details of its 5.2-GHz chip, the fastest microprocessor ever announced. Costing hundreds of thousands of dollars, IBM described the z196, which will power its Z-series of mainframes. The z196 contains 1.4 billion transistors on a chip measuring 512 square millimeters fabricated on 45-nm PD SOI technology. It contains a 64KB L1 instruction cache, a 128KB L1 data cache, a 1.5MB private L2 cache per core, plus a pair of co-processors used for cryptographic operations. IBM is set to ship the chip in September."
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IBM Unveils Fastest Microprocessor Ever

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  • Price: RTFA (Score:5, Informative)

    by miketheanimal ( 914328 ) on Thursday September 02, 2010 @08:03AM (#33447802)
    The Z-series mainframes cost hundreds of thousands (or even over a million) dollars, not the chips. As it says in the article.
  • by Haedrian ( 1676506 ) on Thursday September 02, 2010 @08:05AM (#33447818)

    The thing is that if you have 2 (say) 1.6 GHz processors, they aren't as 'powerful' as one 3.2 GHz processor.

    For one - there are overheads, certain stuff common between them, pipelines - stuff which I forgot (computer engineering related problems).

    But the main thing is that not all programs are multi-threaded, and a program with a single thread can only run on one processor. So yeah, GHz are still useful. Maybe for large single-thread batch processing - which is the kind of thing a mainframe would do.

  • by UnknowingFool ( 672806 ) on Thursday September 02, 2010 @08:42AM (#33448152)
    Unfortunately this chip will most likely go into workstations and servers. In order for IBM to make a desktop version, it will have to make a custom chip to handle things like video, sound, etc. This will lead to same logistical problems for Apple that it had before. Manufacturing companies do not want to keep excess inventories whether it was Apple or IBM. If Apple needs more, it will have to wait while IBM rearranges their manufacturing schedules to compensate. Also even if Apple orders millions of these, it will still be a small customer to IBM; IBM's internal divisions would order more of the stock chip. And the last reason Apple will not go back to IBM; IBM's mobile chip offerings lag way behind Intel's. IBM never made a mobile G5 chip. My guess is that they could never make one that had acceptable power consumption. IBM could do it with enough R&D but again it would be for a very small customer. Not worth enough to the bottom line.
  • by mr_mischief ( 456295 ) on Thursday September 02, 2010 @08:44AM (#33448178) Journal


    It's a quad-core chip. Each core has two integer, two load and store, one binary floating point, and one decimal floating point unit. Up to 24 CPUs can be placed in the frame. It can connect to another whole rack of POWER7 blades running AIX as an application accelerator platform.

    The z196 is for the stuff a mainframe is good at: big batches and fast I/O. The application accelerator is for stuff the clusters of supermicro servers are good at. As a hybrid system connected across the GX bus, it should pump data in and out of applications out pretty well.

  • by bws111 ( 1216812 ) on Thursday September 02, 2010 @09:02AM (#33448362)

    When configured to run Linux, each core costs approx $125K. When configured for z/OS, each core costs approx $250K. A complete system (not including any storage or software) can cost up to around $30M.

  • by valadaar ( 1667093 ) on Thursday September 02, 2010 @09:05AM (#33448392)
    If you direct to the IBM announcement, which mentions the system in more detail then this linked article - http://www-03.ibm.com/press/us/en/pressrelease/32414.wss [ibm.com] The New zEnterprise 196 " From a performance standpoint, the zEnterprise System is the most powerful commercial IBM system ever. The core server in the zEnterprise System -- called zEnterprise 196 -- contains 96 of the world's fastest, most powerful microprocessors, capable of executing more than 50 billion instructions per second. That's roughly 17,000 times more instructions than the Model 91, the high-end of IBM's popular System/360 family, could execute in 1970." 17k x improvement in performance in 40 years? I suppose that is about right...
  • by Ecuador ( 740021 ) on Thursday September 02, 2010 @09:09AM (#33448456) Homepage

    The comments were about the fact that at 3GHz light travels 10cm per clock speed, which limits how far you can have 2 items on a bus if you want them to communicate within 1 clock cycle. There is no "light speed barrier" or anything of the sort, however at these frequencies you design knowing that it will take measurable time for an electric signal to propagate. For example, for this particular system whose core is at 5.2GHz, if you try to send a signal to an external memory that is say 11-12cm away, then it will take about two clock cycles just for the signal to travel the distance.

  • by TheRaven64 ( 641858 ) on Thursday September 02, 2010 @09:21AM (#33448646) Journal

    Wrong chip family. This is the Z-series mainframe chip, using an instruction set that is backwards compatible with the System/360 stuff from back in 1960 (the architecture of the future, as the marketing material trying to persuade my university to upgrade their IBM 1620 put it). The PowerMacs were using PowerPC chips, which use the same instruction set as the POWER CPUs from IBM (they used to be similar, with a common subset, now they are identical).

    The chip that this is replacing, the z10, was designed concurrently with the POWER6. They share a number of common features, including a lot of the same execution engines (both have the same hardware BCD units, for example, as well as more common arithmetic units), but they are very different in a number of other aspects, including the instruction set, cache design, and inter-processor interconnect, because they are designed for different workloads.

    I've not read much about this chip yet, but I think it shares some design elements with the POWER7, in the same way that the z10 did with the POWER6.

    In short, while some of the R&D money spent on this CPU made it into chips that could, potentially, run OS X, this chip itself could not without a major rewrite.

  • Re:Price: RTFA (Score:2, Informative)

    by jtollefson ( 1675120 ) on Thursday September 02, 2010 @10:01AM (#33449378)
    They're very expensive, but for Enterprise scale workloads they're cheaper than the comparable distributed system. The cost entirely depends on how many cores you're running, and more importantly your monthly usage. IBM bills you for your Iron depending on an average of how much you used it that month. There's a reason why Mainframes run so quick and fast, they're the only system where all processing from user ISPF interaction all the way to data processing is tracked. All that processing turns into your final bill with IBM, so upper management has a tendency to pay close attention to usage unlike other systems... But thankfully IBM lets them out on a monthly installment plan. They're kinda like QVC like that...
  • by Jeremy Erwin ( 2054 ) on Thursday September 02, 2010 @10:05AM (#33449460) Journal

    Actually, IBM can upgrade mainframes over the internet. It can also downgrade it, if the lessee so chooses. The extra chips are used for failover.

  • by ledow ( 319597 ) on Thursday September 02, 2010 @10:17AM (#33449714) Homepage

    You could run Linux on it. Then QEMU/WINE combo on that. Then Crysis on that. It'd still probably only get you back to the 2.5-ish-GHz of your average desktop, though.

  • by LWATCDR ( 28044 ) on Thursday September 02, 2010 @10:26AM (#33449882) Homepage Journal

    Banks, Credit card companies, hospitals, Insurance companies...
    Cheap clusters are great but they are not always the best tool for the job.
    Very large traditional datasets involving lots of high value transactions, with 5 9s uptime requirements do not tend to scale well to COTS clusters.
    IBM mainframes have uptimes measured in years if not decades.
    They have hot swapable everything including CPUs. so you can do ugrades with zero downtime.
    Also you need to take a look at the costs involved. The costs to throw out a working software system that has been used for decades and then the cost to redesign it to work on a Cluster of X86 boes will be huge.
    Not to mention the investment in making it fault tolerant and if it is used in certain markets the cost of the auditing the software.
    Not to mention that ZSystems tend to be really secure. There are just not a lot of exploits on Zsystems.

    When downtime can cost millions of dollars hardware costs are just no that big of a deal.
    Now if you are starting from scratch then you may save money by going with a cluster but then you may not depending on just how good your programmers are.

  • by Terje Mathisen ( 128806 ) on Thursday September 02, 2010 @10:29AM (#33449950)

    I guess I'm a counterexample then:

    I'm 53.

    I believe (hope?) most people who know me would say that I'm still a pretty good programmer.


  • by LWATCDR ( 28044 ) on Thursday September 02, 2010 @10:50AM (#33450448) Homepage Journal

    "They say it's an old CISC architecture. This is probably the sort of system that runs horribly outdated and un-updatable code, like the tax system."
    You mean like Windows?
    The X86 is also an old CISC architecture.

    Actually the Power line is RISC anyway. When it is used in a ZMachine the old style 360/370/390 CISC ISA is translated to RISC and then executed.
    Before you go ew that is what modern X86 chips do as well as ARM when using the Thumb Instruction set. The ZSystem ISA is so high end it is almost a high level language so the translation doesn't really effect performance much at all. Also that old CISC architecture is much better than the mess that we have on the X86.
    I am not sure about how IBM does the translation. On the System 38 AS/400 System-I the translation was done during the IPL aka Initial Program Load. On the Zs it may be done as a JIT but I am not sure.
    Honestly I love the idea and wish that Linux would adopt it. You could then have one binary that would work on any Linux system on an CPU.
    The AS400 way kept a native binary copy along with the TIMI copy. When the program was run the first time it would translate the TIMI copy into the native segment. Yes the first time you ran the program it might take a bit to start but after that it would run at full speed and start fast. Of course you could add a binary segment when you first released the code for the ISA of your choice.

    All in all those old Mainframes and Minis had a lot of brilliant tech we still don't have today on our PCs.

  • by root_42 ( 103434 ) on Thursday September 02, 2010 @11:00AM (#33450680) Homepage

    It later mentions using 128Mbyte just for level 1 cache, so that would be around 1024 cores.

    WP has the answer: http://en.wikipedia.org/wiki/IBM_z196_(microprocessor) [wikipedia.org]

    Four cores, 128 KByte L1 data cache, 64 KByte instruction cache.

  • by mikechant ( 729173 ) on Thursday September 02, 2010 @11:14AM (#33450946)

    IBM mainframes have uptimes measured in years if not decades.

    Not in my experience. I can think of at least two factors that require more frequent IPLs.

    1/ Switch back to 'normal' time from DST (e.g. BST to GMT in the UK). Although it's possible to put the mainframe clock forward dynamically (well, change the local time offset actually) sucessfully on many (if not all) systems, in practice most systems will not cope with the clock going backwards (i.e. the 'same hour' happening again) even though the OS supports it. Generally you have to shut the system down for an hour, then IPL. You could probably get away with shutting down all batch initiators and CICS/DB etc. address spaces and then bringing them up again after waiting an hour, but it's typically less risky to follow the established IPL procedure, and this IPL generally obviates the need to have a seperate IPL for 2/; regardless, the machine is effectively down for more than an hour.
    It may be possible to achive continuous operation while moving the time offset backwards with some limited subsets of software but I haven't seen it, and although running on a fixed time and effectively ignoing DST will work, this creates problems of its own and doesn't solve 2/

    2/ 'CSA creep' - tiny bits of orphaned storage (often left by non-IBM supplied products)eventually fill up restricted size critical storage areas such as the CSA, this could lead to an unscheduled IPL, so typically an IPL every (e.g.) 6 months is advisable.

    Not to say that specific systems can't run longer than this (e.g., run on GMT or equivalent at all times, do not tolerate any product which leaks memory in critical areas at all), but I think that's pretty unusual.

  • by knarf ( 34928 ) on Thursday September 02, 2010 @11:37AM (#33451404) Homepage

    Clock rate is no longer the key variable in comparing processors, unless they are of the same microarchitecture.

    Clock rate has *never* been the key variable in comparing processors. Even back in the heady days of 1 MHz 6502/6510 vs 4 MHz Z80 the comparison was useless - the 6510 does way more per cycle than the Z80 and ends up being comparable speed-wise.

  • by LWATCDR ( 28044 ) on Thursday September 02, 2010 @11:53AM (#33451744) Homepage Journal

    It has been a while but really?
    I have never seen a mainframe that didn't use Zulu time. Also in the shop I worked all software was quality verified. One machine was at the five year uptime mark when I left but it was a none commercial system.

  • Re:Price: RTFA (Score:2, Informative)

    by QuantumBeep ( 748940 ) on Thursday September 02, 2010 @12:11PM (#33452114)

    IBM mainframes are leased.

  • by sexconker ( 1179573 ) on Thursday September 02, 2010 @12:27PM (#33452460)

    The word you are looking for is "sleight".
    Sleight of hand.

  • by TheRaven64 ( 641858 ) on Thursday September 02, 2010 @12:29PM (#33452486) Journal

    The X86 is also an old CISC architecture.

    Actually x86 is a new CISC architecture. The System/360 architecture predates it by over two decades. x86 was about the last CISC ISA to be developed outside of a few tiny niches.

    Actually the Power line is RISC anyway. When it is used in a ZMachine the old style 360/370/390 CISC ISA is translated to RISC and then executed

    Umm, no. POWER is RISC (well, RISC purists would say that's stretching the point), but POWER and System/z are completely unrelated. The POWER6 and z10, and POWER7 and this chip, were designed by cooperating teams, so they share some execution units, but they are very different architectures. This is not a POWER CPU running a System/360 emulator, it's a machine with a CPU that happens to have a few pipelines in common with a POWER CPU.

  • Re:Price: RTFA (Score:4, Informative)

    by bws111 ( 1216812 ) on Thursday September 02, 2010 @01:30PM (#33453774)

    You can buy or lease the hardware. The software is licensed under contract.

    It seems like the GP is talking about software charges, not hardware. Software can be either monthly fee based or usage based. If it is usage based you must send a usage report to IBM so they can bill you. That is specified in the contract. In either case, the number of and performance of the CPs is calculated into the cost.

    Hardware is a different story. With hardware, the number of cores you purchase is not the same as the number you get. For instance, you can buy a 1 core machine, but what you get is 16 cores. Only 1 core is enabled in the firmware though. IBM has offerings (again under contract) where you can buy the right to temporarily enable additional processors instantaneously (like if you lost one of your datacenters and need to transfer the workload to another one). With these offerings, you also need to send usage info to IBM so they can bill you for the time that the additional cores have been enabled.

  • by TheRaven64 ( 641858 ) on Thursday September 02, 2010 @02:13PM (#33454500) Journal
    You've almost certainly used some code compiled with a compiler that I've worked on, but I've hardly ever written assembly code, and none of it was in a compiles.

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