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Toshiba To Test Sub-25nm NAND Flash 80

An anonymous reader writes "Toshiba plans to spend about $159.8 million this year to build a test production line for NAND flash memory chips of less than 25 nanometers. The company hopes to kick off mass production of the chip as early as 2012. The fabrication facility for this key NAND flash memory will be located at Yokkaichi, Mie Prefecture."
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Toshiba To Test Sub-25nm NAND Flash

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  • Re:Marginal Gain? (Score:2, Informative)

    by Anonymous Coward on Monday April 05, 2010 @10:52AM (#31733864)

    Well, chips are 2D, so you also get to square that benefit.

    32x32 = 1024 nm^2
    25x25 = 625 nm^2

    That's nearly 18 months of Moore's Law right there.

  • by RabidMoose ( 746680 ) on Monday April 05, 2010 @11:11AM (#31734126) Homepage
    The reason this is a big deal, is that this is the type of flash that goes into SSD's. Right now, a 256GB SSD costs over $600. Read/write speeds on mainstream HDDs are one of the biggest bottlenecks in today's machines, and SSDs are the answer to the problem, once they come down in price. Also, SSDs draw less power than traditional hard drives, so longer laptop battery life is an added benefit. Not to mention the benefit that data centers could see, both from a throughput standpoint, and a lower power/cooling requirement.
  • by TheRaven64 ( 641858 ) on Monday April 05, 2010 @11:22AM (#31734280) Journal

    witch means an approx 4 x larger yield on a 300mm wafer

    I'm not sure what witches have to do with it, but the yield improvement from a process shrink is more than just the 4x that you get from cramming four times as many chips on a wafer. An impurity in the wafer typically destroys one die. If you're unlucky it may be between 2 or even 4. If you make each die smaller then an impurity of the same size may only destroy 1-3 of the 4 in the same area as one of the originals.

  • Re:ultimate limit (Score:3, Informative)

    by RabidMoose ( 746680 ) on Monday April 05, 2010 @11:22AM (#31734288) Homepage
    Actually, it looks like the answer is going to be to step away from silicon, and replace it with graphene []. They can't make it anywhere near as small as silicon (yet), but there's other advantages. The linked article is a pretty good primer on the subject.
  • by ThreeGigs ( 239452 ) on Monday April 05, 2010 @11:30AM (#31734410)

    Shrinking a process gives several benefits, but a quick general overview helps:
    Silicon as used in chip manufacturing is expensive. It costs a lot to grow, cut and polish. It's also a mature industry, so no real breakthroughs are likely to happen to reduce the cost of the silicon. The less silicon area you use, the more chips you can make for the same cost. Next is manufacturing. Whether you put one transistor per square millimeter or 100,000 per square millimeter, the cost is the same, or at least within a penny. Coat, expose to a masked pattern, etch, sputter, clean and repeat a few times, and voila, you have a chip. Shining a light through a mask costs the same no matter the resolution of the mask. Dunking the wafer in a chemical etch bath is the same, running a wafer through a sputterer or CVD costs the same, etc. Labor costs are basically per wafer, so more components per wafer means you get more output for the same labor (and plant infrastructure) dollar.

    So, a smaller manufacturing process means:
    More components per wafer. Thus if you double the component density, your manufacturing costs will remain the same, and you can double output while keeping costs the same (think 32GB for the price of 16GB).

    You can also make the chips smaller while keeping the same capacity (same 16GB chip uses half the silicon, thus costs 50% less to make, think 16GB for half the cost you paid last year).

    Or, more capacity within given size limits. (think 64GB or 128GB SD cards, or 2 TB Compact Flash).

  • A litho primer (Score:2, Informative)

    by quo_vadis ( 889902 ) on Monday April 05, 2010 @12:24PM (#31735202) Journal
    For those unfamiliar with the field of semiconductor design, heres what the sizes mean. The Toshiba press release is about flash. In flash, the actual physical silicon consists of rectangular areas of silicon that have impurities added (aka. doped regions or wells). On top of these doped regions, are thinner parallel "wires" (narrower rectangles) made of poly silicon. The distance between the leading edge of wire and the next is called the pitch. Thus, the half pitch is half that distance. The reason this is important is that half pitch is usually the width of the polysilicon wire and effectively becomes the primary physical characteristic from the point of view of power consumption (leakage), speed and density.

    The official roadmap for processes and feature sizes (called process nodes) are published yearly by the International Technology Roadmap for Semiconductors, a consortium of all the fabs. According to the 2009 lithography report []. 25nm Flash is supposed to hit full production in 2012, thus inital deployments happen a couple of years before. Effectively Toshiba seems to be hitting the roadmap.

    The takeaway being, theres nothing to see here, its progress as usual. The big problem is what happens under 16nm. Thats the point at which current optical lithography is impossible, even using half or quarter wavelength, and EUV with immersion litho.

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