Sun Plans Security Coprocessor For New Ultrasparc 59
angry tapir writes "At the Hot Chips conference at Stanford University, Sun presented plans for a security accelerator chip that it said would reduce encryption costs for applications such as VoIP calls and online banking Web sites. The coprocessor will be included on the same silicon as Rainbow Falls, the code name for the follow-on to Sun's multi-threaded Ultrasparc T2 processor."
Encryption != Security (Score:5, Insightful)
A chip to offload encryption is a good thing, however it is not a "security chip". Security is a broad topic that this chip will barely touch.
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Keep it simple.
Their target market is VoIP and banking websites, where SECURE Sockets Layer/Transport Layer SECURITY rule. (Okay, with VoIP they're more of a pipe dream, but work with me here...") Those are what the chips are designed to accelerate by offloading. VoIP *does* (or can) use MD5/SHA hashing, which is also something accelerated by the chip.
Thus, calling it a SECURITY accelerator doesn't confuse the people that sign the checks, because SECURE and SECURITY are what they're already using for the
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Again, the people that understand the difference don't need it explained to them. Those that don't -- the ones that sign the checks -- will just be confused. Now, even more so if you bring up trusted execution.
Sun's been doing encryption offload since well before Via added it on their chips. This is just a new revision of their crypto accelerator board. Personally, I've been using these [soekris.com] for years. Cheap and effective.
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You're making a fundamental mistake. You're assuming that the terminology applied by the vendor is meant to be descriptive. Its only purpose is to persuade people that they want to buy it.
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They do, actually if I recall correctly in T2 they have one per core, where each consists of 3 cells each consisting of two n-well resistors (thermal noise essentially) connected to an amp which feeds into a VCO (voltage controlled oscillator) that gets sampled with regards to a different clock.
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A chip to offload encryption is a good thing, however it is not a "security chip". Security is a broad topic that this chip will barely touch.
Encryption takes the failure of a breach out of the responsibility of the computer and makes the greatest point of failure the human being.
That is much as we can hope for.
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Bingo (Score:4, Funny)
"At the Hot Chips conference at Stanford University, Sun presented plans for a security accelerator chip that it said would reduce encryption costs for applications such as VoIP calls and online banking Web sites. The coprocessor will be included on the same silicon as Rainbow Falls, the code name for the follow-on to Sun's multi-threaded Ultrasparc T2 processor."
Any experienced buzzword bingo player should have shouted out before reaching the end of the first sentence.
Difference from the T1/T2 on-chip cryptography? (Score:4, Interesting)
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That's right. I don't understand what is new here aside from marketing spin.
Re:Difference from the T1/T2 on-chip cryptography? (Score:5, Funny)
As I understand it, the T1 and T2 chips both have on-chip crypto accelerators (one per core) already - what's the difference...?
Well, here it is as I understand. In T1, Arnold came back to terminate Sarah Connor and was unsuccessful. However in T2, Arnold was reprogrammed by future John Connor to defend his younger self. This cemented Arnold's historic status as both among humanity's greatest villains and greatest heroes of all time. And in California, because we love that stuff, these events ensured victory during his bid for power in the 2003 Governor Recall election.
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Re:Difference from the T1/T2 on-chip cryptography? (Score:4, Informative)
The T1 and T2 have different cryptographic capabilities. See page 5 of "Using the Cryptographic Accelerators" [sun.com] a description. I would imagine that they are including even more support.
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Not much difference, it's just third iteration of in-CPU crypto accells. See details in presentation [sun.com].
Re:Difference from the T1/T2 on-chip cryptography? (Score:5, Informative)
The T1 only has hardware to help with the initial key exchange. SSL traffic starts with an RSA key exchange using a a huge public/private key and then uses a block cypher like DES or SHA or RC4 to encrypt the data using the key that was exchanged via the RSA encryption. The T1 can't do block cyphers quickly and only has the first part speeded up. I found that my amd based X2100 would catch up to the T1 based T1000 after about 3000 bytes of an SSL stream and then quickly pass it. I've been told that the T1 was supposed to have block cypher hardware but maybe it was buggy and was disabled. Anyway sun should kill the T1 since its slow and expensive. Maybe thats their intent with their new T3120 but few details have been released.
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I wonder what will happen when "hackers crack security chip"? lol
"World Awash In Magic Smoke"?
Unanswered Questions (Score:2, Interesting)
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"This history of co-processors for specific jobs has never been a very happy or long-lived one."
Seems to me that GPU's have been around for a pretty long time, are generally pretty successful at what they do, and people are more-or-less happy with them. Perhaps, though, they are the exception that proves the rule.
Re:Unanswered Questions (Score:5, Insightful)
How will current software interact with this chip and be transparent for current applications? Software support in things like IPSec libraries for this hardware is going to be important.
This is Sun. They sell the whole stack - computer, OS, compiler, and so on. You can bet that Sun Java running on Sun Solaris, running on a Sun UltraSPARC will use the coprocessor. The Solaris version of OpenSSL almost certainly will too.
Is this a response to the Sparc's lack of CPU grunt compared with other processors? If it is then it's going to make Sparc even more expensive relative to the competition.
Not sure how you figure that. Something like the OMAP3530 can decode H.264 in a tiny power envelope compared to something like a Core 2, and yet costs much less. Why? Because it uses dedicated silicon for the decoding. General purpose processors use much more power and, for the same transistor budget run much more slowly than dedicated hardware. If the typical workload for a T2 is very crypto-heavy then adding a dedicated a crypto coprocessor will use less power and give better performance than adding another core. This is why most ARM chips include a number of coprocessors for workloads that are common in handhelds.
It's easier to update software than it is to update silicon or chips. How will this approach and this chip fare in a few years when technology and software has moved on?
But it's slower to replace standards than either, and encryption standards require years of peer review before they are approved.
This history of co-processors for specific jobs has never been a very happy or long-lived one.
Yup, no modern CPUs contain on-chip floating point or vector coprocessors. Well, none except for all of them. And no modern computers contain graphics coprocessors.
It looks like a way of making up for the inherant lack of grunt on the Sparc platform, so maybe it will reduce encryption costs as far as that platform is concerned.
Not sure what you mean by 'inherent lack of grunt'. For highly parallel workloads (e.g. web serving, lots of database workloads), there isn't much that beats a T2 in terms of throughput at the moment, and nothing that comes close in terms of performance per Watt. Offloading to a coprocessor improves power efficiency even more, which is something that people running data centres care a lot about.
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Why is this even on Slashdot? Its so un-news worthy, as pointed out by the previous commenter, this is the rule, not the exception these days. I had a paper at HotChips 10 years ago that presented an onchip crypto accelerator when it was actually a fresh idea. A more interesting discussion is perhaps whether payload encryption for applications such as VoIP belongs as an instruction set enhancement or as a stand alone co-proc. Many current chips that implement crypto co-proc's fail to utilize the true potent
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Hmmmmm. So Sun are turning the Sparc platform into a specific platform for specific purposes with specific processing for specific tasks? Doesn't really sound like a computer to me so I don' know where you're going with that. It's a bit of a daft comparison. I was referring to Sparc's lack of performance when compared with the competitor that has a
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How will current software interact with this chip and be transparent for current applications? Software support in things like IPSec libraries for this hardware is going to be important.
This is Sun. They sell the whole stack - computer, OS, compiler, and so on. You can bet that Sun Java running on Sun Solaris, running on a Sun UltraSPARC will use the coprocessor. The Solaris version of OpenSSL almost certainly will too.
Yes, of course, through their pkcs#11 provider, to be precise. Any application that can use PKCS#11 will be able to use this acceleration. Of course, *some* configuration will likely still have to take place. Java is actually pretty good already, you can simply add a security provider to the top of the list to accelerate any application. OpenSSL can work through PKCS#11 engine nowadays as well.
Is this a response to the Sparc's lack of CPU grunt compared with other processors? If it is then it's going to make Sparc even more expensive relative to the competition.
Not sure how you figure that. Something like the OMAP3530 can decode H.264 in a tiny power envelope compared to something like a Core 2, and yet costs much less. Why? Because it uses dedicated silicon for the decoding. General purpose processors use much more power and, for the same transistor budget run much more slowly than dedicated hardware. If the typical workload for a T2 is very crypto-heavy then adding a dedicated a crypto coprocessor will use less power and give better performance than adding another core. This is why most ARM chips include a number of coprocessors for workloads that are common in handhelds.
Yeah, and don't forget that transistors are pretty cheap compared to going for the latest chip technology/speeds.
It's easier to update software than it is to update silicon or chips. How will this approach and this chip fare in a few years when technology and software has moved on?
But it's slower to replace standards than either, and encryption standards require years of peer review before they are approved.
Yu
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I think Sun is gambling that the thready goodness of the new processors + the crypto coprocessors = something you want to buy.
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How will current software interact with this chip and be transparent for current applications? Software support in things like IPSec libraries for this hardware is going to be important.
If a piece of software uses OpenSSL, OpenSSL needs to be modified to use the hardware instead of doing computations the normal way (e.g. using instructions on the main processor). Some functions inside the library are being deferred to the hardware, for example the computation of a checksum.
Generalized accel, or specific algo's? (Score:2)
Anyone know if this is a generalized solution, or an implementation in silicon of specific algorithms? I'm not terribly fond of the idea of specific algorithms being implemented in silicon, simply because, what happens if a weakness is found in the algorithm(s) being used, and they need to be changed? There was an article posted not too long ago to slashdot, about someone beginning to find weaknesses in AES. One of the problems with 'fixing' any flaws found in AES (one 'easy' solution being proffered in tha
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It already exists in T2, with "Eight encryption engines, with each supporting DES, 3DES, AES, RC4, SHA1, SHA256, MD5, RSA-2048, ECC, CRC32" (From http://en.wikipedia.org/wiki/UltraSPARC_T2 [wikipedia.org])
Also, the T2 has hardware random number generator.
The T2 processor seems to be designed with web serving in mind, and especially makes an excellent SSL enabled web server.
I fail to see why this is newsworthy, as the T2 already does this quite well, and few people seem to care.
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If only there was some sort of array of logic gates, that was fully programmable.
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Making programmable hardware, or general-purpose hardware is easy. Making dedicated hardware that is fast and low power is easy. Making general-purpose hardware that is fast and low power is very difficult.
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Why would you want a dedicated chip for this when cloud computing is in fashion? Offload your burdensome encryption work.
Yeah, this is *exactly* the sort of hardware that the "cloud" providers run.
but is Oracle interested? (Score:2)
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You can still provide the whole stack without being in the incredibly expensive and highly competitive CPU business.
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