IBM's New Processors To Exceed 5Ghz 250
Jordin Normisky writes to mention the news, via ZDNet Asia, that IBM's new Power6 processor will be unveiled next month at a conference in San Francisco. They're also planning to announce a second-generation Cell, both of which are expected to run faster than 5GHz. From the article: "In addition, the [Power6] chip 'consumes under 100 watts in power-sensitive applications,' a power range comparable to mainstream 95-watt AMD Opteron chips and 80-watt Intel Xeon chips. Power6 has 700 million transistors and measures 341 square millimeters, according to the program. The smaller that a chip's surface area is, the more that can be carved out of a single silicon wafer, reducing per-chip manufacturing costs and therefore making a computer more competitive. Power6, like the second-generation Cell, is built with a manufacturing process with 65-nanometer circuitry elements, letting more electronics be squeezed onto a given surface area. "
Manufacturing Cost has little to do with it... (Score:3, Informative)
The smaller that a chip's surface area is, the more that can be carved out of a single silicon wafer, reducing per-chip manufacturing costs and therefore making a computer more competitive. Power6, like the second-generation Cell, is built with a manufacturing process with 65-nanometer circuitry elements, letting more electronics be squeezed onto a given surface area.
The cost of making chips, by far, is the R&D cost. The "first" chip costs hundreds of millions to make. Once the "first chip" is made the margin cost is VERY low. Beyond recovering R&D costs....the rest is just distribution channel costs....then....PROFIT!Re:And here I thought... (Score:5, Informative)
"I carry a 1 gallon bucket and run around in circles 5,000,000 times a second. I'm faster!"
"I carry two 1 gallon buckets and run around in circles 2,500,000 times a second. I'm faster!"
Re:We've heard that before. (Score:2, Informative)
These are the engineers, including at least one IBM Fellow (the second author)... this is not the PR department. I expect these folks would not take their reputations in the engineering community lightly.
Re:Work-per-clock cycle? (Score:4, Informative)
Re:65 nm hardly to brag about (Score:5, Informative)
Re:And here I thought... (Score:5, Informative)
Opteron 3.0 2119 706.3 2365 788.3
Intel P4 3.8 1834 483.4 2091 550.2
Intel Core2 2.66 2848 1070.6 2673 1004.8
IBM Power5 2.1 1747 831.9 3324 1582.8
I gave myself a headache trying to read your table, I hope you don't mind. I also apparently missed the 3GHz Opteron launch in '06...but things still don't look good for AMD.
Re:And here I thought... (Score:5, Informative)
Re:Someone please explain cpu clockspeeds (Score:2, Informative)
Anyway, here goes:
Basically they take a tiny wafer-thin piece of silicon, use chemical to scrape out millions of little transistor shapes onto its surface, and strap a buckin' bronco of a clock crystal on it that shakes it like a salt shaker, or like jello jigglers on free-based cocaine.
Thusly, the outrageous oscillating action of Mr. crystal causes the tiny transistorized citizens to go into a tizzy, but they're all right because they're not hollow and fragile like vacuum tubes, so they get all busy and start swinging their logic gates open and shut kind of like an electron square dance.
The speed that the crystal is eventually set at is the maximum speed at which the transistors can go about their daily lives, such as munching on electrons and crapping them out, organising meetings, forming PTA (parent-transistor association) clubs, and dipping into the cache without generally spontaneously combusting or reverting back to silicon amoebas. Each time the crystal wiggles its booty constitutes one clock cycle, and the number of operations per cycle varies based on the processor and the types of instructions the poor transistors must labor over.
Clock speed has been historically limited by various things, including level 2 cache memory timings (remember this stuff has been running at CPU speed for about 5 years now!), motherboard design, pipeline depth, heat dissipation, ALU and/or FPU limitations, or even the leakage the P4 was subject to at 4GHz+ clockspeeds. Right now I believe it's the fault of lazy hardware engineers at Intel and even AMD. Dual-core and quad-core is an easy out for expensive, fast-sounding hardware just like it is for the video card market right now, and the burden of performance improvement has been shifted to software engineers (reducing bloat, multithreading applications, both of which can only go so far). IBM is hopefully going to prove this with a higher-clocked POWER chip or two that maintains the efficiency they have a reputation for, although we may never see the return of single-core CPUs for performance systems.
Re:DRAM latency/bandwidth or interconnect? (Score:3, Informative)
Re:Size matters (Score:3, Informative)
* software for synthesis, implementation, timing/physical/formal verification, OPC, power/temp analysis and all the other stuff runs in the millions of dollars.
* 20 engineers working for 3 years + benefits/managers/other overhead ~10 million dollars.
* mask costs 100's of thousands of dollars.
so getting to the first chip runs at least 15-20 million dollars and for something like the core2 duo it's closer to 500 -1000 million.
the next wafer only costs a measly 10k
Re:And here I thought... (Score:4, Informative)
Some more information (Score:5, Informative)
The Power6 processor will run between 4GHz and 5GHz and it has been proven to chew away data at a speed of 6GHz in the lab.
IBM see things a little differently and they decided to raise the frequency in both cores of the processor.
For high-end models, four POWER6 MPUs will be packaged in a single multi-chip module, along with four L3 victim caches, each 32MB.
On the management side, IBM is also improving their virtualization capabilities in the POWER6. In particular products, a single processor may be able to host 2-300 virtual instances, although theoretically up to 1024 VMs are possible. Memory partitioning and migration have been added as well, which reduces system down time for repairs.
IBM is claiming a factor of two performance increase, which would be consistent with the vastly higher clockspeeds and increases in raw system bandwidth.
IBM's roadmaps currently include the POWER6+, which is presumably a 45nm derivative product. Judging by past practices, the POWER6+ will debut in the second half of 2008, probably just in time to dash the hopes of rivals.
The Power and PowerPC lines will grow one step closer together with Power6, which incorporates the AltiVec instruction set that speeds up many multimedia tasks. AltiVec, also known as VMX, increases efficiency by letting a single processing instruction be applied to multiple data elements. That's helpful for video and audio tasks on desktop machines, but servers will benefit as well in, for example, high-performance computing tasks such as genetic data processing, McCredie said
Where Power5 can transfer data on and off the chip at a rate of 150 gigabytes per second, Power6 can do so at 300GBps, McCredie said.
Oh, and it is also good for BCD's (binary coded decimals) which obviously points to the expected customers (high end financial firms, presumably).
Sources:
http://news.softpedia.com/news/New-Power6-IBM-Pro
http://realworldtech.com/page.cfm?ArticleID=RWT10
http://news.zdnet.com/2100-9584_22-6124451.html [zdnet.com]
Re:And here I thought... (Score:3, Informative)
More cores means more threads, which is all fine and lovely, unless you really need a single thread to do something very quickly. Perhaps the algorithm that you are implementing doesn't parallelize well, for instance.
Re:And here I thought... (Score:1, Informative)