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Hardware Technology

Reduce Transistor Power Consumption 124

Posted by ScuttleMonkey from the so-i-rewired-it dept.
revelCyllufyalP writes to tell us that University of Kentucky researchers have discovered a way to reduce the overall power consumption of transistors. From the article: "In order to improve computer chips' performance, transistors' size and gate insulators have to be continuously shrunken so that more components can be packed into a single chip. Computer chip producers were hitting a wall in downscaling the transistors and gate insulators because of their inability to reduce the leakage current of the existing gate insulators. This new technique will help the chip producers to develop more powerful chips with low-power consumption."
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Reduce Transistor Power Consumption More

Reduce Transistor Power Consumption

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  • Woohoo (Score:4, Interesting)

    by matr0x_x ( 919985 ) on Wednesday December 07, 2005 @01:46AM (#14200224) Homepage
    This may not sound like that big a deal, but let me assure you this is very significant to wireless infrastructure enhancement. One of the biggest limiting factors in wireless devices is power consumptions, so this is great news for the industry!

    • Re:Woohoo (Score:3, Informative)

      by 0racle ( 667029 )
      How could this not sound significant to the general users of this site. The latest Athalons and Pentiums use how much power again? If these guys patent this idea, I'm guessing it could make them quite rich.
      • It may not make a big difference with the high-frequency chips like gigahertz CPUs. Semiconductor power consumption is mainly two components: static DC consumption and dynamic capacitance load. The gate leakage current is what makes static DC consumption high, but at high frequency, dynamic capacitive load dominates the power consumption, because you are charging/discharging billions of tiny capacitors at the speed of 1 trillion times a second. It's kinda like switching to drive and reverse gears in a car
    • W00t! Now they can put those low-power tracking devices in our necks.
    • There are three reasons why this will not have a big impact on wireless devices.

      First - other than the digital parts of the device usually BJTs are used which have a leaky base as it is so improving the MOSFETs will not do anything for the BJT parts of the circuit.

      Second - even if you make the whole device with MOSFETs the real power consumption is in parts like the transmitter and receiver which have orders of magnitude more current going through them than the leakage current.

      Third - most wireless devices

  • How do you reduce tunneling current? (Score:5, Interesting)

    by Beryllium Sphere(tm) ( 193358 ) on Wednesday December 07, 2005 @01:49AM (#14200231) Journal
    The press release says they're getting several orders of magnitude less tunneling current through gate insulators. But tunneling happens because some portion of the electron's wavefunction extends to the other side of the insulator. Whst are they changing that would affect the physics? Or are they fixing a different kind of leakage and getting the press release wrong?
    • Tunneling is a function of both the physical width and potential energy height of the energy barrier. Obviously, they don't want to increase the width. I don't know the details, but I would surmise Warning ... he's making this up ... that their process simply increases the (height of the) potential barrier from drain to gate.

    • Re:How do you reduce tunneling current? (Score:5, Informative)

      by soundsop ( 228890 ) on Wednesday December 07, 2005 @02:29AM (#14200350) Homepage

      It's easy to reduce the tunneling current through the gate. All you have to do is increase the thickness of the insulator. Unfortunately, this has the detrimental effect of reducing the effective capacitance of the gate, which in turn lowers the amount of current conducted by atransistor of a given size (lowering the current also lowers the speed). To make up for the lowered gate capacitance, researchers have been trying to increase the dielectric constant of the insulator. I'm guessing that they're proposing a method to increase the dielectric constant of the gate insulator. The devil is in the details of improving the dielectric constant without screwing up later processing steps or reducing the mechanical integrity of the wafer, etc.

      Summary:

      1. To lower gate leakage simply increase dielectric thickness.
      2. To make up for lost speed due to higher dielectric thickness, increase dielectric constant.
      3. Profit.

      • Re:How do you reduce tunneling current? (Score:5, Funny)

        by saifatlast ( 659446 ) on Wednesday December 07, 2005 @03:38AM (#14200500) Homepage
        I'm no expert, but even I can see that you missed a step here. Here, I'll fix it for you.

        1. To lower gate leakage simply increase dielectric thickness.
        2. To make up for lost speed due to higher dielectric thickness, increase dielectric constant.
        3. ????
        4. Profit

        Hope that clears things up for everyone.
      • I thought that using CMOS tech. the larger the gate capacitance is, the lower the speed, since you have to "charge" that "capacitor" in order to deliver a signal.

        Increasing the gate insulator would in turn, perhaps affect the electric field strength required to create or deplete the SourceDrain Tunnel - which in turn, requires more current -> higher power consumption.

        So these guys found a way to reduce leakage current without increasing the insulator size...?

        Or Am I getting this wrong?
      • This is basically true. But preventing leakage is not just due to the thickness of the insulator. The inevitable flaws in the insulator, and the unevenness of its formation, are a big source of leakage. Just as eggs stick to the pan and burn where you failed to put enough cooking oil, you can fix it by adding more oil (which you may not want to do on your diet), or by heating the pan first and swirling the oil around to spread it evenly before you add the eggs.

        The process these gentleman describe involves s
      • Actually to get faster people are trying to reduce the capacitance with low-K dielectrics. Not increase (hint: more capacinance = more charge to transfer = slower switch; if you can transfer less current to turn the switch on, it'll work faster). The reason to thin the gate is partially to do with Vp (propagation delay) issues, partially to do with just making the device physically smaller and partally (if I remember this bit of semiconductor physics correctly) to do with getting the gate polysilicon itsel
      • You can also increse the energy neded to transpass the insulator. that will reduce the leakage current maintaining its thickness. Of course, you need a better insulator for that. And discovering what is this "better insulator" is a huge problem, and buiding it on a chip, another problem as big as the first one.
    • The tunneling goes through different kind of defects in the oxide material (crystal imperfections impurities etc). I guess in this case the RTA (rapid thermal annealing) improves the oxide quality by removing the crystal imperfections ( by rearraging the oxide in high temperature) and maybe by gathering the impurities by diffusion...
      • Sorry to nitpick, but the SiO2 formed for typical gate oxides would be fused silica (semi-amorphous) not crystalline SiO2 (quartz crystal). Although they don't mention the specifics, typical RTA schemes only take the wafer to about 1100C, and the divitrification process of going from silica to quartz drops to an almost zero rate below that. So, assuming they don't super-heat the wafer (there would be a lot of resulting issues with any previous Silicon diffusions, and I thought quartz had worse gate-oxide p

    • Physics (Score:5, Informative)

      by kf6auf ( 719514 ) on Wednesday December 07, 2005 @04:01AM (#14200566)

      A quick lesson in quantum physics:
      Basically, tunnelling occurs because an electron can get from one side of a potential barrier to the other without ever being in the forbidden region (the width of the barrier, where the potential energy exceeds the total energy of the electron) due to it existing as a wavefunction that does not collapse until you observe it. Anyway, the chance of an electron penetrating a simple potential barrier like the gate of a transistor is a function of the height of the barrier (voltage applied to the gate), the width of the barrier (gate length), and the energy of the electron (voltage across transistor + electron thermal energy).

      So ways to decrease tunnelling include:

      • Longer gate, but slower. Wanting smaller transistors and faster speeds is the whole reason we're having this problem.
      • Increase gate voltage or decrease transistor voltage. Unfortunately these two are coupled. They might not exactly cancel each other out, but they make things difficult.
      • Decrease the thermal energy of the electons. There are a couple ways to do this. One involves liquid nitrogen; the other involves something like making electrons climb further out of their holes to become free (fairly easy by introducing impurities into the silicon), resulting in less electron energy and so less tunnelling. Also less current in general though, so this might be prohibitive for some other reason.

      Just my $0.02 since if I knew for sure I'd be making 6 figures somewhere and not applying to grad schools...

      • The leakage path relevant to tunneling is through the gate oxide, from the gate to the channel below it. In this case, the width of the barrier is the gate oxide thickness, not the gate length. So the ways to decrease tunneling include having a thicker gate oxide, but of course it'll still be slower (less capacitive coupling of the gate to the charge in the channel). A representative paper reviewing gate tunneling and its effects on logic gate performance is this one [stanford.edu] (in pdf).

        Also, the height of the barr
      • Nice post (generally a breath of fresh air when we see one of our own).

        Something I'm a bit surprised that no one has mentioned yet is the capacitance of the p-n junctions in the transistor. Don't forget changing the dielectric constant and the potential has an effect on this aspect of the component as well. To people asking "how important is such a capacitance?" Well, the capacitance causes frequency dependent behavior (you have just introduced an RC time constant).

        An area where I have dealt with thi

    • I'm attending ISDRS in Bethesda this week and presenting a paper tomorrow. It was interesting but I'm not entirely sure how well it would work. I'd have to see the actual data (which usually isn't shown in such presentations) and try it. It had to do with passivating the oxide-silicon interface with deuterium instead to reduce the number of hot carriers injected through the oxide. My review: interesting but I want to repeat it and see it in action.
  • If Intel could apply this technique to existing P4 chips that burn ~150 watts what would the savings be? 10,000 - 100,000x less leakage current is how much of the equation?
    • haha why would they apply it to the P4 wouldnt that be a waist of time... look at their new processor line power consumption 108 watts @ peak
    • considering the fact that static (leakage) power should be
      the real killer in microprocessors is the dynamic power - for wireless/dsp/ucontroller type applications, it could be pretty huge

      honestly, the article has so few details it's impossible to tell what they're really doing, but i am pretty sure that most companies out there already use RTP on there gate oxide...
    • Actually, Intel has their own solution to this problem [reed-electronics.com] - redesign transistors out of different materials that switch faster and consume less power.

  • Prior art? (Score:5, Funny)

    by Dirtside ( 91468 ) on Wednesday December 07, 2005 @01:53AM (#14200239) Journal
    University of Kentucky researchers have discovered a way to reduce the overall power consumption of transistors
    Wayyyy ahead of you. [uc.edu]

  • Where's the news? (Score:5, Interesting)

    by Anonymous Coward on Wednesday December 07, 2005 @01:58AM (#14200255)
    As probably one of the few semiconductor geeks on /., I have to say: Where's the news? Gate dielectrics are always made with rapid thermal processing on current technologies. Basically, stick a wafer in a chamber, flow some gas, turn on some super-high intensity
    lamps, heat the wafer to >1000C for a very brief time, grow a few atomic layers of silicon dioxide (or some variant that includes nitrogen), turn off lamps, cool wafer, take it out of chamber.

    From what little info is in the press release, it doesn't sound like they're doing anything revolutionary, so I'm curious why they claim they can reduce gate leakage by so much.

  • It is already done, old news (Score:4, Interesting)

    by karvind ( 833059 ) <karvind@NoSPAM.gmail.com> on Wednesday December 07, 2005 @02:00AM (#14200266) Journal
    Gate oxides in current microprocessors are around 1.2-2 nm and are grown using RTP (rapid thermal process). A furnace oxidation is too fast. So yes industry already uses rapid thermal anneal (as suggested in TFA) for their gate oxides. Can anyone tell how is the new ?

  • Cuts 75% of power usage in current generation (Score:5, Insightful)

    by Markus Registrada ( 642224 ) on Wednesday December 07, 2005 @02:02AM (#14200274)
    In the latest generation of processors, 50% - 75% of the power consumption is this gate current leakage. In the next generation, it was looking to go over 90%.

    What this really means is that the next generation has just become possible. As an incidental side benefit, current-generation laptops will be able to run cooler.

  • Must be late... (Score:3, Funny)

    by cagle_.25 ( 715952 ) on Wednesday December 07, 2005 @02:03AM (#14200277) Journal
    Heh...for just a second as my eyes hit the headline, I thought that the researchers had discovered some "direct tunneling" from Kentucky to the United Kingdom.
    • They did. Shhhh.

      We had to change the title quick like after the truth was printed.

      Cant have that getting out.
    • ummm... twins!?!?
      • Twins are separate organisms; there's no point of confusion *unless* they are conjoined, which I would consider to be a boundary case. Fair?

        • Twins are separate organisms; there's no point of confusion *unless* they are conjoined, which I would consider to be a boundary case. Fair?

          Ouch! What the GP was mentioning with twins though, is that your sig "Human being (n.): A genetically human, genetically distinct, functioning organism." (emphisis mine)

          According to that definition, maternal twins (triplets, etc) would not qualify as a Human Being since each one is not genetically distinct ... on the other hand perhaps we can look at it as a "Human B

          • I wasn't trying to be cold-hearted about conjoined twins; I was just imagining a situation in which it might be difficult to discern how many organisms are present. In practice, it may be that all such cases are lethal abnormalities, so that all living cases of conjoined twins are clearly two organisms.

            With regard to normal twins, I agree that the language doesn't parse nicely. I'm not intending "distinct" to mean "unique", but simply "distinct from other organisms which might be present and attached." S

            • Didn't think you were trying to be cold hearted. I actually thought you were trying to make a pun about co-joined twins being a 'boundry case'. :)
    • Ah so they lower consumption by plugging into 110V instead of 240 ?

      I'm not sure that's the best potential application for their tunneling system. :)

  • size vs heat (Score:5, Informative)

    by esac17 ( 201752 ) on Wednesday December 07, 2005 @02:09AM (#14200295)
    What you have to remember about heat is that electronics only get hot because they are never perfect conductors nor perfect insulators {though we can make nearer-perfect insulators than we can conductors}. A perfect conductor will never get hot, no matter how much current you put through it, because the voltage drop across it will be nil and power = voltage * current. Nor will a perfect insulator, because this time, the current through it will be nil.

    CMOS is based around two transistors, a P-channel FET which goes conductive when the gate is driven low, and an N-channel FET which goes conductive when the gate is driven high. The P-FET is trying to pull the output high and the N-FET is trying to pull it low. Both the gates are joined together, and this is the input. This is a simple NOT gate.

    For a NAND gate, where any input 0 will drive the output to a 1, we have several P-FETs in parallel trying to drive the output high, and so many N-FETs in series trying to drive the output low. Each P-FET gate joined to an N-FET gate is one input. When they are all high, all the N-FETs turn on allowing the output to go low; when any one is low, the chain of N-FETs is broken, one or more P-FETs turn on, and the output goes high. For a NOR gate, where any input 1 will drive the output to a 0, we put the Ns in parallel and the Ps in series. You can make AND gates from NAND+NOT, OR gates from NOR+NOT, and any other combination you like. In fact you really don't need both NAND and NOR, because you can make either one out of the other; but it turns out they're equally as easy to make as each other in CMOS {not like many other technologies}.

    In an ideal world this would never dissipate any power, since the input cannot be high and low at the same time so only one of the transistors will ever be on. In practice what happens is that the gates act like capacitors which take a finite time to charge and discharge. They do not switch instantaneously from conductive to non-conductive. So one stops conducting while the other is starting to conduct, and for a brief instant while the inputs are changing state both transistors are conducting a little. It's not a dead short circuit of course, otherwise something would give way ..... hopefully a fuse.

    Now every time something changes state, you get a little pulse of heat. Which is why fast processors need cooling. Additionally, to make sure that the logic gate output has changed state before the next clock pulse, you need to make the gate capacitances charge up quickly -- which means using a higher voltage than you could get away with at lower speeds. But 2x more volts means 2x more amps means 4x more watts.

    Smaller transistors should have less gate capacitance, and so be capable of switching more quickly.

    • Re:size vs heat (Score:5, Interesting)

      by soundsop ( 228890 ) on Wednesday December 07, 2005 @03:32AM (#14200490) Homepage

      Some clarifications:

      Short-circuit current is only responsible for 10-20% of switching power. The rest is dissipated in the transistor through charging and discharing all the nodal capacitances (due to transistor gates, transistor diffusions and wiring capacitance). Since typical circuit styles are non-adiabatic, this charge/discharge power component would not go away even if we could completely eliminate short-circuit currents.

      Making transistors smaller certainly reduces their gate capacitance but it also reduces their current drive by the same proportion. These two effects cancel each other out! So how can transistors get faster from generation to generation?

      Transistors get faster by increasing electron mobility and/or increasing gate capacitance per unit area and/or reducing diffusion junction/sidewall capacitance per unit area/perimiter and/or reducing (local) interconnect capacitance since smaller transistors are closer together.

      • Making transistors smaller certainly reduces their gate capacitance but it also reduces their current drive by the same proportion.
        Are you sure? As I remember, let's say we take a transistor and halve every dimension. By C=(8.8542 x 10-12 K A)/D this will halve the capacitance. Now we've halved the conduction channel though, so at constant ohms/square (as is a fair model for most FETs in the conduction region) then the resistance of the channel stays constant. Assuming we keep the same drive voltage this

    • Re:size vs heat (Score:5, Insightful)

      by william_w_bush ( 817571 ) on Wednesday December 07, 2005 @04:29AM (#14200621)
      Great comment.
      The unfortunate corrolary to:
      Smaller transistors should have less gate capacitance, and so be capable of switching more quickly.
      is:
      Smaller transistors will have less resistance, and so will dissipate more power.


      Which is why the P4 prescott, while a marvel on the drawing board, is pretty crappy in reality. 90nm technology has largely been an attempt to find a happy medium between higher capacitance and lower resistance, both of which limit speed. The current "nucular age" of chips is a direct by-product of ignoring the drop in resistance until it was too late.

      Also, at 4+ Ghz an current-induced EM field has many of the properties of a microwave beam, which can resonate, and essentially self-focus on any imperfections in the semi-conductor structure, essentially burning small holes in the chip, or causing signal noise unless perfectly grounded (which in itself causes inductive leakage). This is why intel and amd have speed-bins, because the chips with the fewest imperfections are able to perform at the highest clockspeeds without thermal or electric failure.

      My point is, the mega-hurts race, even assuming one or more miracles of metal-oxide chemistry, is ending. I look forward to the multi-proccessing race which seems to be heating up, as a long-postponed, but neccessary next step. The sad obstacle holding back the day of 1000-thread chips has been programmers complete lack of willingness to move beyond the single-threaded debugging paradigm. As one myself, I understand why it's seen as hard as it is, but consider it more of a viewpoint shift, rather than an insurmountable increase in complexity. New languages/language changes will happen to simplify threaded programming, and new mechanisms like auto-synchronized data structures, self-unrolling iterands, and integrated message-passing stacks will replace old-standbys. The mega-threading doomsday scenario will fall along the wayside with other past programmer nightmares such as the death of the goto loop and the loss of direct memory access in java and higher level languages, left only as subjects of nostalgia.

      Clockspeed is dead, long-live multi-threading.
      • Yes, power dissipated is V*V/R or VI And yeah, smaller transistors have lower resistance. But smaller gates mean less power, not more. You need less current to move the charge in and out of a smaller transistor (since the charge is smaller). So the "I" in the "VI" can go down. Well, that "I" is really a "V/R" (current across a resistance), so lowering that I really means you can reduce the "V". And since the total power is V*V/R, that means the total power used drops drastically.

        Let me explain it a little b
        • a: I think I misspoke. When I said that at smaller feature size, resistance goes down, I was also considering leakage as a failure of resistance. You're right, the current 90nm designs do use less power, the amd design in particular because it uses SOI to compensate for increased leakage, while I don't believe intel has soi on its chip line yet. At these scales, execution tends to matter as much as size, and my earlier point of blindly scaling down in hope of finding more gains from the magical process shri
          • Even a 1GHz non-multithreaded chip can be much faster than a 4.0GHz Prescott today. It doesn't take threads to best it. All you have to do is jettison all the transistors that you absolutely can do without (16-bit mode, out of order execution) and then replace them with transistors you can use.

            If you want to run code across a family of processors, you'll have some wastage of transistors. This isn't avoidable. But it is also critical. You can't just make one CPU and throw it away, you need a family to compet
            • Good reply.
              I'm not trying to write-off chip speeds, but as a programmer I'm aware we can't just count on the fact that this bloated, single-threaded program/game which slugs around now will work fine 1 year from now when the processors catch up.

              Second, multi-chip cpu's do work, the gpu is essentially a graphics slave to the primary, specialized for its tasks, with access to primary memory, and using specialized (tho with need of improvement) mechanisms to offload work from the cpu. TCP offload adapters are
              • I probably wasn't clear enough about what I meant by multi-chip CPUs. And I probably interpreted your original description too rigidly to mean the thing that isn't viable anymore.

                Let me explain.

                It used to be that you might have multiple chips involved directly in the execution of the instruction stream. For example, the AMD 2900 series was bit-sliced. When an instruction was fetched and executed, multiple chips worked on it in parallel. I don't know the restrictions, but I believe each chip operated on 8 bi
        • > A 1000-thread (simultaneous) chip is a ridiculous idea.

          Strong claim. One must ask: Why?

          > That means you have to duplicate every transistor in the chip (like registers) 1000 times.

          And this is bad... how?

          > That makes no sense.

          It makes enormous sense when you're running 1000 threads!

          > You will never reach the same speed as current single processor chips with a 1000-thread CPU
          > (at least not right now).

          Naturlich, since the latter is a figment. But supposing it were real, one would have to as
      • Clockspeed is dead, long-live multi-threading.

        So true. Nature "figured this out" long ago. For proof, check out the massively parallel machine that is your brain. It would be interesting to make a simple processor that could be tiled ala VLSI and interconnected to its neighbors or a center controller. Massive multi-threading will work best when the hardware matches the software concepts.

    • Re:size vs heat (Score:3, Interesting)

      by elgatozorbas ( 783538 )
      They do not switch instantaneously from conductive to non-conductive. So one stops conducting while the other is starting to conduct, and for a brief instant while the inputs are changing state both transistors are conducting a little.

      Even if they don't EVER conduct (even a little) at the same time there will be dissipation because the capacitance is charged and discharged all the time. Each of these cycles implies that some positive charge moves between the power supply and ground with the capacitor as a

  • "It was really simple," said the researchers at the University of Kentucky. "We siply asked the Flying Spaghetti Monster to fix the problem for us, and He did." </flamebait>
  • As speeds increase, won't leakage also increase because the insulators are, in effect, capacitors? At RF speeds, power flows through capicitors.

    I'm not a chip designer, just a ham radio bug, so I don't know if this problem has already been found to be a non-issue. Maybe one of you bright guys knows the answer?

    • Re:Chip insulator sas capacitors? (Score:1, Informative)

      by Anonymous Coward
      You can use a high-k dielectric and get the same capacitance as a SiO2 layer. A good looking material is HfO2. Keep in mind that as transistors are scaled, the capacitance is scaled too -- thus your natural increase in speed.

      The leakage is normally due to direct tunneling. Basically the silicon dioxide layer is so thin and the electric field is so high that electrons tunnel between the gate and the source/drain.

      I think all this paper is about using some sort of thermal processing to make a higher quality ga
    • Power doesnt really flow through capacitors.....they just support a charge being moved either side of them. When that moving charge does work like speakers or antennas, then yes, there is power consuption.

      MOS transistors have acted like capacitors for ages. There's no power flow in the sense of work done, there is just the regular expense of charging/discharging the gate.
      • Of course power flows through capacitors! You've got charges, you've got voltages, you have that charges flowing from one side to the other with a voltage on them in a certain amount of time, charge * voltage / time = power. If you couldn't transmit or modulate some power, you couldn't transmit or modify a signal. That's basic thermodynamics: if you can't transmit power, you can't transmit a signal.

        The "work done" is, to some extent, recoverable when you change the state of the MOS transistor by discharging
        • Is this not a case of terminology problems?
          Power "flowing" is a horrid concept. Current flows, power is a measure of work done.
          So no a capacitor will do no work (well, capacitors do get hot, but that's the resistive component of their physical construction). If you attatch a perfect capacitor to your AC supply most power meters will register power consumed (after all they're doing V*I) even though the transistor isn't dissapating any heat itself. The point being that the current is out of phase with the vol
  • Anyone know? For once Wikipedia [wikipedia.org] isn't much help.

  • PlayfullyClever, eh? (Score:5, Interesting)

    by Ospeovedizer ( 85934 ) on Wednesday December 07, 2005 @03:22AM (#14200457)
    So, did ScuttleMonkey not notice that the submitter's name was PlayfullyClever backwards? The one whose website says that the vast majority of /. posts are "blatantly plagiarized"? Although the news seems real enough to me, the submitter's name and website raised some pretty big alarm bells, especially since their site now says:
    "okay, so we are going to win slashdot again, this time with a different game plan, keep your eye out for our new name.. it is VERY playfully clever."
    Hmm... As I said, the news seems real enough, but the submitter is a fake.

    • Re:PlayfullyClever, eh? (Score:2, Informative)

      by Anonymous Coward
      i checked the program at the 2005 International Semiconductor Device Research Symposium (http://www.ece.umd.edu/isdrs2005/program.html/ [umd.edu]) and sure enough, today at 4:35 PM, their paper is being presented: Dramatic Reduction of Gate Leakage Current of Ultrathin Oxides Through Oxide Structure Modification, Zhi Chen et. al, University of Kentucky
    • The submitter is not a "fake". On their site they are quite up-front and honest with their tactic. The real problem is that the slashdot editors are morons and don't give a shit.

      -b

    • Re:PlayfullyClever, eh? (Score:4, Informative)

      by Surt ( 22457 ) on Wednesday December 07, 2005 @10:02AM (#14202039) Homepage Journal
      I don't really see how it's possible for the submitter to be fake. Either he submitted the story or he didn't. Apparently, he submitted the story.

      Now, he might think the joke is that he's posting 'news' from a news aggregation site to a news aggregation site, but meta news is the only kind of news slashdot gets anyway, and that's what we come here for.

      All in all, if he's scamming slashdot, he can only be doing it if EurekAlert is a fake, which it certainly doesn't look like at first glance, though I notice that in an unusual move for a meta-news site, it doesn't have links to originating information. That is somewhat suspicious. Still, if true, it's an incredible effort he's putting in just to scam slashdot stories.

      Further, it would have to be a long term scam plan, since the UKY story in particular is real:
      http://news.uky.edu/news/display_article.php?artid =844 [uky.edu]

      So at best he's trying to build credibility as an article submitter for a later scam.
      • I don't really see how it's possible for the submitter to be fake. Either he submitted the story or he didn't. Apparently, he submitted the story.

        He submitted the story until you view it, at which point, he didn't.

  • Other Applications (Score:3, Insightful)

    by EBFoxbat ( 897297 ) on Wednesday December 07, 2005 @05:35AM (#14200774)
    Assuming they really have discovered a way to lower power consumption (forgive me for not understanding semi-conductor principles) would it not be applicable to other semiconductors? I immediately thought about cell phone/mp3 player battery life and other such things. Even so far as to think about laptops. I (roughly) understand the not-so-much-wasted-power train of thought, and heat reduction from a CPU core and all, but wouldn't this have just as much effect on battery-powered devices? Or am I just being an ass again?
  • ...would be a great start. Most modern COTS CPU fans crap out in 2-3 years, tops, but I have a dual PentiumPro 200 box under my desk which is showing no sign of wearing out a fan after ~10 years of continuous service.

    Let's not even discuss my underengineered AOpen laptop with its hopelessly inefficient (and now defunct) fan, other than to say that bypassing 75% of its heat generation would be -ing marvellous; the hard disks might also last more than a year, and the battery be worth something again (maybe wi
  • Although I'm sure these guys are top-notch, research isn't what comes to mind when I think of Kentucky.
  • From the little information provided in the article, it appears that this takes care of the gate leakage problem, which is great! However, it doesn't address the Source-Drain leakage, which is a larger issue for current process technologies. Gate leakage isn't forseen to be a significant problem until 45nm.

    This just tells us that future technologies are not going to have twice the leakage power as current technologies. This doesn't mean that future process technologies are going to have less leakage pow

  • so KFC now means Kentucky Fried Chip?

    *ducks*
  • Out of curiousity and because I have been trying to figure this out ofr some time now....why don't they just make the processors bigger? Looking at an old PIII I have laying around, it's 2 in^2. I'm sure P4's aren't that much smaller. What if they bumped it up to 2.5in^2 or 3 in^2? then they wouldnt have to worry about making the transistors smaller because there would be all that extra space. If there is any flaw to my theory, please let me know because in my mind, it seems like a very good solution....
  • The article was purposefully mum on the technique these guys are using, so I'll try to elaborate:

    We all know that the fab process for turning silicon into chips is *way* too complex to be explained by ordinary science, so the UK researchers instead brought in 7 Christian ministers to sanctify the process. Prior to etching, the wafer (pun intended) is doped with a mixture of holy water & oil. As the etching process takes place, the ministers intone the "Reverent Petition for Holy Quantumness" in q

  • Terrible news for cooks (Score:3, Funny)

    by petantik f00l ( 926671 ) on Wednesday December 07, 2005 @04:00PM (#14205089)
    This news has made me very depressed.

    how can I now be a cook at the same time as programming?

    Before my Pentium 4 generated heat enough for frying eggs and I'm sure in a few years I would be looking for recipes suitable for heat generated by nuclear reactor( charcoal egg comes to mind) but now me dream is gone. Damn you University of Kentucky researchers. I hope we never meet
  • UK researchers - damn! Just when I thought us Brits might be making scientific progress again!

    Still, great tagline for the UoK though.

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