Anyone Using JHDL for Programmable Logic? 153
gte910h asks: "I
am an embedded developer who is learning how to program programmable
logic devices (CPLD's and FPGA's). I have looked at VHDL and other
Hardware Description Languages, but they seem so obtuse compared to C
or Java. Has anyone tried any of the tools based off of general
purpose programming languages, like JHDL.
Do they work as well as VHDL and other HDL's? These would make things
this type of development acessable to more people if they work well
enough." Are packages similar to JHDL available for other
languages?
VHDLs are good for you! (Score:1, Offtopic)
JHDL, now -- let me guess: Just-right Height Density Lipoproteins? Sure sounds good to me...
;)
HDL 'programming' (Score:5, Insightful)
Both VHDL and Verilog have their strengths - you'll get used to them. Especially if you have to sit down and hand-tewak the resultant logic aftewards
Re:HDL 'programming' (Score:3)
Inefficient logic is the least of your worries. "Programmers" that are new to HDL's have a tendency to think linearly, which is a Bad Thing(tm). You end up linear dependencies (i.e. X must happen before Y), and sometimes even *loops* which are the worst thing you could possibly do in HDL. Since almost everything is happening in parallel in most code snippets, the code simply doesn't work properly in hardware. Some gates will initialize properly, others will be zero, and most everything else will be in a random state.
My microprocessor design professor used to mock CS students ("see...you have this *object*...) because of the poor code they produced. Don't be one of those people, but instead "think hardware" when you're writing HDL.
Re:HDL 'programming' (Score:2, Interesting)
The 'conceptual model' that is embodied in high-level languages such as C/Java or Verilog/VHDL couldn't be more different:
It's not surprising that people (such as the poster of this story and the students you mention) have trouble shifting between them.
Re:HDL 'programming' (Score:2, Informative)
The non-procedural Verilog vs. procedural C did confuse her for a little while, but she caught on pretty quickly just like I did.
You just have to take a little time to explain what "=" is versus "<=".
-prator
Re:HDL 'programming' (Score:3, Informative)
I actually like to sometimes use a verilog coding style that's more close to co-routining where the synthesis tool creates a hidden state variable for you however you have to check with your tools to see if they'll accept it [synopsys does] - old time verilog hacks throw up their hands when they see this stuff. Event when I'm not using this style and making my state machines by hand I still tend to write verilog that looks much more like traditional programming (fewer larger always statements that
do lots of things together) - my experience has been that this makes me much more productive (I can turn out >100k aggressively timed, DV'd gates per year of relatively random logic).
Recently I made the move back to doing more software - I've found my kernel driver coding skills are greatly enhanced by my time writing gates - stuff that might have been hard to find in the past is instantly obvious today because I've spent all that time designing stuff that cared implicitly with time
Re:HDL 'programming' (Score:2, Informative)
Easy to write vs easy to debug (Score:3, Informative)
About a year back I began doing some work in Verilog, because it was common in the area. Next chance I got, I switched to VHDL. Both languages were learned from scratch. The C vs Pascal comparison for Verilog vs VHDL is rather apt. I found that mistakes in my Verilog design would lurk much later into the build process, whereas most mistakes in my VHDL design would show up much sooner. With conventional programming, the difference may not be that great, because compilation isn't that 'thick' a process. With hardware design its much worse, with several stages of synthesis, timing, and only after that do you get into place and route. Some of my Verilog mistakes didn't show up until place an route, where I never had a VHDL mistake make it past synthesis. These are even mistakes that make it through simulation. HDL can be subtle indeed, especially for a newbie.
To some extent this comes back to the old C vs Pascal debate. Unfortunately Pacal was crippled by the limited library and other factors of its definition, so the debate could never be truly intelligently done. There's a tremendous amount of "Real Programmers..." macho crap in the debate too, further reducing the intelligence level. (training wheels references, and all that.)
Today we gripe over and over about buffer overflows, and wonder why they keep happening. It comes down to this: The C language is perfectly happy to let it happen, so preventing buffer overflows is completely up to programmer diligence. While you can probably come up with a buffer overflow in Pascal descendents (Gotta include that 'descendents', since pure Pascal is *practically* useless, I agree.) it almost takes work. No doubt there would have been no end of griping about that max_length on the strings, but then that's pretty much what needs to be done by hand for C.
Ada currently carries the Pascal-descendent banner, and is still alive with a reasonably vital community. Oddly enough, the US DOD has largely abandoned it, thinking C/C++ leads to cheaper development. Much of the new Ada community appears to be European, by the way.
The insiders' view appears to be, "Yes, it's more of a pain to develop the code, and that takes longer. But you buy all that back and more when it comes to debug and maintenance."
Re:Easy to write vs easy to debug (Score:2, Interesting)
VHDL has so much overhead and is cumbersome to write in in my opinion. Verilog also seems to generally simulate faster. Also the free (GPLed) icarus verilog simulator is better than any free VHDL simulator I've been able to find :).
Also when it comes to writing behavoural testbenches I could never live without fork/join.
Lastly many of the deficiencies in verilog have been corrected in the Verilog 2000 spec.
Re:HDL 'programming' (Score:2)
Re:HDL 'programming' - JHDL can help! (Score:2, Informative)
JHDL has advantages that you attribute to both VHDL and Verilog. Because it is based on Java, it is much easier to debug than a C-based HDL. Java is also much easier syntactically than VHDL OR Verilog.
JHDL is structural. In JHDL, you describe your circuit using java classes to represent circuit components - for me very intuitive. If you want an AND gate, you instance a new AND gate.
Also, it is very easy to write parametric circuits in JHDL - i.e., an arbitrary-width adder.
JHDL currently does not have a "finished" synthesis tool, but it is currently being worked on. So in the future you will get the best of both worlds - a powerful structural description and synthesis capabilities...
Re:HDL 'programming' - JHDL can help! (Score:1)
Yes, it's good to be able to instantiate an AND gate when you need it, it's more productive to move beyond schematic capture when you don't really need to instantiate gates.
VHDL has the generate statement and generics so it supports parametric circuits quite well, and easily enough. Verilog can do it too but it's a kludgey mess compared to VHDL. One can do it with the help of macro preprocessors and parameters.
Nothing against JHDL. I guess I just don't see what it brings to the table that ain't already there.
Re:HDL 'programming' - JHDL can help! (Score:2)
As for structure. All HDL's will have some method for describing structure. VHDL uses the entity as the most common hierarchial component. A entity has a well defined interface, and may use generic parameters. In addition you can use blocs for describing smaller subcomponents and configurations for describing the overall system. (One very useful propery of VHDL is that you can have multiple implementations (architectures) of an entity. A configuration is used for selecting the apropriate one)
Genericity along with generate statements make it very easy to describe very general structures. Good for reuse.
From what I gather of JHDL is that it tries to be a behavioral description language rather than an HDL. This poses a problem at synthesis as behavioral synthesis is a lot tougher and more error prone process than rtl synthesis (though improvements are beeing made)
I don't really see at first glance what this particular language might offer (though it might find a slot in dynamically reconfigurable circuits, (which is rather margial IMO)).
VHDL, Verilog and "those other languages" (Score:4, Informative)
VHDL has a much richer syntactic set than Verilog; however, it's easy to lose track of some of the features, and most synthesis tools need to convert to Verilog for gate-level representation of the code eventually. Some companies (such as Altera, with AHDL) have created hybrid languages that add some of the features to VHDL to Verilog; Verilog 2000 (which does the same, but isn't as widely proven yet) is another option. Still, if you want a simpler HDL than VHDL, I'd recommend Verilog.
The languages derived more directly from C and Java (SystemC, for example) are even less tested; it's hard to tell what bugs or other shortcomings exist in the tools. C and Java were designed without concurrent structures, and this makes me suspect HDLs derived from them will actually be more awkward than VHDL or Verilog.
Re:VHDL, Verilog and "those other languages" (Score:1)
Re:VHDL, Verilog and "those other languages" (Score:2)
I thought the same thing. I'm also an embedded programmer. And while I don't design PLDs and probably won't write a line of Verilog during my career, I have had cause to peek at the code and I've found Verilog to be very readable. (After, of course, a quick 5-minute-or-less introduction to the language by one of the EEs.)
Re:VHDL, Verilog and "those other languages" (Score:4, Informative)
Jean Ichbiah... (Score:2, Insightful)
Re:VHDL, Verilog and "those other languages" (Score:1)
Thank you for your comments, but the Ada FAQ [adapower.com] (see section 2.6), a timeline [fit.edu] of the language's history, and a writeup for a UMich course [umich.edu] suggest otherwise. While S. Tucker Taft may have led the Ada 95 revision team and Jean Ichbiah led the Cii Honeywell Bull team designing the submission to the DoD (which became Ada 83), the design of the language is clearly not the work of a small number of people.
Rather, it was designed to meet a specification from a DoD working group and received feedback from hundreds of reports (and dozens of individuals or other groups).
While Robert Dewar's answer to "Was Ada designed by a committee?" is certainly witty, a rose by any other name would smell the same. Taft's answer lists -- for just Ada 95 -- not only the core "Design Team," but five other full- or nearly-full-time teams ("Language Precision Team", "Requirements Team", and three "user/implementor" teams) and the large group of "Distinguished Reviewers."
Given all that, I will retract my description of Ada as being designed by a committee -- it was in fact designed by a beauracracy!
(As for VHDL, I cannot find as detailed information on the web about its history, and don't have my VHDL books with me right now. However, the timeline at the University of Erlangen-Nürnberg's VHDL-online [vhdl-online.de] -- with discussions and defining requirements taking up most of a decade -- suggests that it suffered from too many cooks at times.)
While I agree that Ada and VHDL are very expressive and powerful, it's not good to get rose-colored glasses about their history or (especially in VHDL's case) drawbacks.
Re:VHDL, Verilog and "those other languages" (Score:1)
Intuitive? Ada? (Score:1)
They tell me that the running wage for good Ada programmers is well over $100k/year. Some get 2-4 times that. Perl programmers don't generally get that much, but I'd rather do Perl than Ada because it is so anal-retentive. If you want to make sure your airplane doesn't crash due to software failure, use Ada. For anything else, find another language.
Ada may be stable, but anal-retentive verbosity does not intuitivity define.
Re:VHDL, Verilog and "those other languages" (Score:1)
[SNIP]
The reason for mentioning VHDL as opposed to Verlog is probably that he's a european HW designer. European designers use VHDL and everyone else uses Verilog.
BTW: I'm studying electrical engineering at Technical University of Denmark [www.dtu.dk] and I've never written a single line of Verilog - none of the professors teach it since it would be hard to get a job in europe.
And Canadians learn both... (Score:1)
If you've wired logic by hand with 7400-series TTL (like I have), HDL's come quite naturally. They're NOTHING like a computer programming language.
Grab a copy of klogic or something similar and play with digital design before you learn an HDL. You'll do much better design as a result.
Re:VHDL, Verilog and "those other languages" (Score:1)
HEH (Score:4, Funny)
This just reminds me of the differences in thought between EE and CS...
HDL's in java or C? HEH... What's next? x86 assembler implemented in java? ( pun
Maybe you should take a look here http://philip.greenspun.com/humor/eecs-difference
Damn CS's
BTW... (Score:2)
I did not mean C-like syntax..
I am aware of verilog and other hdl's with "c-like" syntax...
but the way he worded that question seemed to imply something very different
You are so right (Score:2)
Damn CS majors...
You're thinking EE and SE (Score:1)
Computer Science is different. Computer Science is more like: compilers, OSes, the Halting Problem, P and NP, etc. We look at asymptotic bounds, amortized algorithmic performance, etc.
We look at a different class of problems.
Slow down Cowboy (Score:2)
VHDL tends to the standard (Score:3, Insightful)
Last year, I was in a FPGA-based hardware design class, and during the early course of our group's project, we thought that maybe we'd be better served by switching to something easier to use. Long story short, we wasted three weeks trying to learn the "simpler" method which nobody at our school used, while the other groups plowed through VHDL, which everyone at the the school used, and they ended up with a better result.
I'm not saying "Because its the most popular it must be the best," but user base realy is a major decision when trying to go a particular route.
Celoxica DK1 (Score:1, Interesting)
Re:Celoxica DK1 (Score:1, Interesting)
In terms of productivity and time to market, JHDL/VHDL/Verilog/SystemC are dead in the water.
The real difference... (Score:1)
BugBear
Toto - This doesn't loook like C (part deux) (Score:3, Insightful)
There is a reason that it looks "obtuse" to you. The language is built to describe parallel things, i.e. stuff occuring at the same time, and at a VERY low level. As others have mentioned, it's built for EE work not CS work.
If you want something that is more C like, then look at verilog. I picked up verilog in 4 days and was producing useful hardware descriptions. I maybe have one advantage over you though. I'd been using pal programming languages like ABEL for 10 years before I ever saw Verilog. You might say my head was already in the right space.
If you want a free verilog compiler that covers 95% of the languages capability check out www.icarus.com
Write Java and get gates? (Score:4, Informative)
They seem to have gotten some fairly decent speed/area results.
Re:Write Java and get gates? (Score:1)
As far as making bad chips, again I invite you to try it out before you make such blanket statements. "Those who say it can't be done should stay out of the way of those who are doing it!" (or something like that...)
ya i remember... (Score:1)
JHDL is supposedly good, but lacks in synth dept. (Score:2, Informative)
The problem, i understand, is synthesis (the process of making hardware out of your source files). JHDL seem to lack those, but things might have changed...
So remember to check out the synthesis tools before you commit to JHDL....
SystemC vs. HDL Languages (Score:3, Informative)
But, if you're doing any kind of sizable project (like designing parts of supercomputers, for instance) then you'll just have to bite the bullet and learn how to design logic. VHDL is a little screwy, but Verilog is a breeze to learn and use. Just like you can't fake being a programmer, you can't fake being a logic designer. Just learn the background, there's no way around it.
When in Rome...
Re:SystemC vs. HDL Languages (Score:1)
compiler pile-up (Score:1)
JHDL (Score:2, Insightful)
Also the only reason you would have problems in VHDL is if you didn't understand how it works. When I got started in it I found I had to forget all the programming I learned and move into describing my circuts instead of trying to program their behavior. You'll find this type of mindset works well with VHDL/ABEL/Verilog.
OMG (Score:1, Funny)
Embedded Developer (Score:1)
"I'm an embedded developer."
As a Comp Sci Student. (Score:2, Insightful)
I actually enjoy VHDL. I found it extremely easy to use once I realized that I wasn't actually programming I was just drawing with words.
Granted I was doing fairly simple things, (junior level Computer Organization class), but VHDL didn't seem obtuse at all to me.
Hardware is not Software! (Score:4, Informative)
For the whole chip we used nothing but if-else, case, the usual boolean operators (and, or, xor etc.) and shifters. That's pretty much all you need. Loops, multi-dimensional arrays etc. aren't needed AND the synthesis tools will often either reject them flat out or construct very strange logic from them.
In order to "get" VHDL, you need to pretty much abandon all your software habits. Think in terms of parallel operations, not serial ones. Also, draw timing diagrams! They can be a real life saver.
Our company bought a soft IP core from a third party about a year ago. We got the VHDL source and everything. We tried to synthesize it and the tools eventually did it...but it took 14 hours. So, a few of us took a look at the code. What we saw horrified us. It was written in VHDL, but it was written in an extremely "software" like manner. A week later, we had re-written most of the offending blocks. The result was that the design synthesized in 4 hours and was 20% smaller.
Hmmm...I had a point in there somewhere, but it seems to have turned into a long rambling story.
Remember, coding hardware in an HDL is, and will probably never be, the same as writing software!
Parallelism and J[ava]HDL (Score:3)
The difficulty is that Java is a serial language for designing software to execute on a serial processor. HDL's target devices that are inherently parallel, and have the extra complexity and difficulty that comes with that. There is currently *no* compiler that can get good performance out of serial HDL's. It's a different programming paradigm; you might as well ask for LISP that looks and feels like C. Even if you match the syntax, you still have to change paradigms to get any useful work done.
The area this targets (I believe) is unified design, where hardware and software (such as it is) for embedded devices is specified in the same language. They want to go for reconfigurable computing, you know, the one where you can perform parallel 1-bit additions twenty thousand times faster than a P4. Thing is, targetting hardware, which is inherently parallel, you need a language that supports that parallelism. J[ava]HDL just won't work, period.
Re:Parallelism and J[ava]HDL (Score:1)
They are using Java objects to instantiate gates , flops, and wires. There's hierarchy so an object can be a collection of other objects which is ultimately made up of gates, flops, and wires. In other words C = A + B looks like:
VHDL: C = A + B
Verilog: C = A + B
JHDL: adder(A,B,C) where adder , in turn is a glob of discrete gates.
Frankly, I don't see the point. I could make netlists in any number of languages. I don't have a burning need for a new one. It's not adding anything new and in some ways is a step back. For example, to do a multiplexer, it seems that I would have to instantiate one:
multiplexer(A,B,S,C)
While in Verilog or VHDL I could use a nice case or if-then-else.
if (S == 1'b0)
C = A;
else
C = B;
And instantiating a mux is better/easier/clearer how?
We must obey the synthesizers (Score:3, Informative)
However, there are really only two companies that make very high quality synthesizers: Cadence and Synopsis. Having used both of their products, I have to say that they only design for two languages: VHDL and Verilog.
And I must say, I don't blame them. Trying to extend Java to create hardware is crazy; they have to do a workaround in order to create multiple inheritance, as well as justifying the use of functions to specify IO properties of certian wires.
Syntax is sort of irrelevant, both VHDL and Verilog don't make this blunder. A function should not determine the properties of a signal - it makes a lot more sense that the only thing that functions can do is change the value of said signal.
Also, someone might try to use Java primitives that simply confuse the issue. VHDL has very basic support for primitives, which is very tied to bit manipulation (as well it should be, since each bit represents a single wire). Java isn't nearly as good without adding some non-inuitive (in Java) functions to the mix.
VHDL is not very close to ADA, despite a few slight syntactic elements. Verilog is not C, despite the same. They are HDLs, well suited to their tasks.
One final point: those languages (Ada and C) make good starting points for other languages. ADA provides the necessary strictness to ensure hardware design is not sloppy - a necessity since sloppiness results in errors and most hardware errors are impossible to detect during runtime. C was designed to be a low-level language, and to interface well with low-level operations, making it particularly well suited to the design of low-level systems. What other language makes a better starting place for a new languages design than these two based upon these lingual goals?
Re:We must obey the synthesizers (Score:1)
Synplify is made by Synopsis, dude. Synopsis is a company, not a tool.
And for this argument, it doesn't matter how VHDL compares to Verilog. I was comparing both of them to JHDL, and basically stating that the only real choices for HDLs are Verilog and VHDL.
Also, I tend to believe you're wrong about the "verilog is more popular" argument. I use VHDL because more companies have VHDL packages than Verilog packages for the work that I've done, so that I can test my designs in VHDL before synthesis. Also, I've been able to find a lot more information about VHDL. Perhaps Verilog is more popular with the people you've worked with.
(On a side note, I think Verilog is way too simple - it makes you work at the lowest levels when you don't have to do so. You don't have to because components are already available that can do a very good job).
Learn VHDL (Score:2, Insightful)
I think verilog has been mentioned already so I'll skip that (it's just VHDL lite IMHO). VHDL is around for a reason - it's about the maximum level of abstraction that's reasonable. High level (>=C) are great, but they work because microprocessors are designed to work with abstact structures. Hardware is just designed to work (usually). Think about it this way - if you want to program in C, program a *computer*, if you want to design hardware, keep in mind that you're designing hardware and *not* programming a computer.
If I'm totally off-base, and you were actually complaining about VHDL's crappy syntax (ON CLOCK'EVENT et al),just learn it - it's not bad at all once you get down to it, and it does make sense after you've used it for a while. (I hated it too when I first started).
Some thoughts from a JHDL developer (Score:5, Interesting)
One semester, the EE department decided to use JHDL as the HDL for the logic design class (then it was EE320), and I was the teaching assistant that "specialized" in the actual tool (JHDL). Basically, JHDL was used as an introductory HDL for the students. The results were interesting.
In short, most of the class succeeded in building an LC2 processor entirely in JHDL, interfacing it with memory, and programming it (netlist, run through Xilinx backend tools, transfer bitstream) onto a Spartan chip. Most of the issues arose in the students struggling with object-oriented programming (creating a "Wire object" and a "2:1 Multiplexor object") and in the subtle details of how to interface circuit components with one another. A lot of students would get sections of their circuits ripped out by the Xilinx tools for failing to simply attach one component to another. The schematic viewer, waveform viewer, and other debugging tools proved effective in helping with the actual design.
Automated and dynamic simulation is easily performed in the simulator GUI and in testbenches. There is a Finite State Machine generator. There is parameratizable Floating Point arithmetic unit (its size depends on the number of wires you pass to it when you instantiate it; there are many more modules like this). Parameters can be assigned to the circuits in JHDL to, for example, instruct the Xilinx tools how to assign pins to top-level wires. Multiclock functionality exists. My DRC subsystem can dynamically instantiate circuits and run user-specified (and user-defined) checks on those circuits through a GUI. JHDL is fairly sophisticated, and it is an impressive tool given that it is mostly a student-developed application.
Before I left the lab (I had a very heavy classload), we were kicking around the idea of making JHDL Open Source. There are many legal issues we had to deal with... I'm not sure how it's looking now.
my experiences with VHDL (Score:2, Informative)
And keep in mind that there are various levels of abstraction that you can use for VHDL. If you're going do to the gate level it's going to take you some good time to learn it but your chips will save money because they are smaller/faster/more efficient. Even if you don't learn the most abstract parts of the lanugage, you can still program the gate logic using C-like logical operators (which saves you huge amounts of time compared to cad tools where you have to connect the gates manually.)
The moral of the story: Spending the time to learn VHDL will pay for itself. The big chip manufacturers like Xilinx control large market portions, and their tools are VHDL-centric.
VHDL is good (Score:3, Insightful)
I am a programmer and digital hardware designer with 10 years experience in both areas.
I find that VHDL, while obtuse, is a terrific modeling language. There is a steep learning curve associated with it. Once you get the hang of it, it can do many things for behavioral modeling and RTL design of FPGA's and ASIC's.
It has been said that once you pick up VHDL, Verilog is easy to pick up afterwards.
It really depends on what you are trying to do. Are you trying to realize a design into an FPGA? For example, VHDL code is written differently when modeling behavior. When you're using VHDL to implement a real design for an FPGA, the coding style is different and many techniques you've learned in CS do not apply here. Good coding practice still applies such as well definied variable/signal names, proper data typing, generous use of white space, and verbose comments. However, that is where the similarities between C coding and VHDL coding end.
The real issue here with VHDL design to an FPGA are the tools. How well the tool that you've chosen (i.e. Synopsis Design Compiler or Synplicity's Synplify) reads in your VHDL, parse it, and create a gate level design using the low level building blocks available for a given FPGA/ASIC family.
Because of this, the code needs to be written in a specific way. To implement a counter, you would need to write a specific construct that the synthesizer recognizes.
But, that is just the beginning of your problems, there is no real good way to have a synthesizer infer that you want a ripple counter, compact counter, balanced, and so on. The only way to get exactly what you want is to define it gate by gate, what connections are connected to what. This provides for zero ambiguity how the design is to be implemented in an FPGA and you gain something such as performance or decreased utilization (there is a trade-off somewhere). In my experience, I find that synthesis tools try to find a happy middle.
The problem as I see it with the JHDL and other languages that try to supplant VHDL/Verilog is that they haven't matured. You will be hard pressed to find adequate tool support for those languages. Synopsis provides support for System C (if I recall correctly) but Synopsis products are horrendously expensive ($60K a year MAINTENANCE fee alone). Recently, EETimes reported that EDA companies are generally not happy with System C right now as its touted benefits don't seem to be happening.
Should you choose something other than VHDL/Verilog, your choice of platforms may be limited as well, such as using Solaris which are not cheap. It depends on your outfit, can they afford the cost and be on the bleeding edge or is it a shoestring outfit scraping to get by where it can (i.e. affordable FPGA tools on affordable platforms)?
There is the long term to consider. If you were to successfully develop a FPGA design utilizing JHDL for the first generation. What happens if support for JHDL disappears when the time comes to do a 2nd or 3rd generation of your design? The long term outlook for languages other than VHDL and Verilog are unclear.
Hope this adds some insight to your questions.
It looks interesting... (Score:2, Insightful)
...people are making good points that hardware is not software. Everything is happening at the same time and if you are thinking in a one stream of execution state of mind you are not thinking in the correct problem space. The virtual machine that is presented by most operating systems is simply nothing like hardware. Not to say its bad, its just different.
No support (Score:2, Informative)
HDLs have their place (Score:2, Informative)
I have seen numerous designs done by primarily FPGA designers which use the languages (esp VHDL) very liberally, which usually works fine for programmable devices where the compilers can make your code work as long as it fits and meets timing, but when you want to put that code into an ASIC, it's a nightmare (non-synchronous design, no thought about DFT). Just like when doing OO programming, you need to THINK about your design or objects first, then code it up in C++ or VHDL _last_. It's a "description" language. HDLs should be used to describe designs that have already been designed in your head or on paper. The synthesis tools can do very funny things with code that is even functionally correct but just syntactically awkward. Sometimes, you just have to write the HDL in a manner that gets you what you want from the synthesis tools. Sometimes, good code in = garbage out! Writing code in high level languages puts another layer of complexity into the problem.
We are currently investigating some of the new tools that are starting to pop up out there for high level hardware design. It appears to me that using high level languages makes the most sense when you want to do functional type designs, for instance, DSP chips. There it makes PERFECT sense: you describe your DSP functions and algorithms in C just like you would if implementing it purely in a software application, and the tools can translate that into a decent HDL description for a signal processing core. Other things which are more structural than functional, are better done in one of the HDL languages. But we'll see. Doing circuit design in high level languages like C and Java is a New Thing(tm) and so the performance of these tools yet on really large and complicated designs isn't well known yet.
But if you want to learn HDLs, I would recommend starting with Verilog. It's based on C and is syntactically much less complicated than VHDL. Verilog is also faster than VHDL when doing large simulations. And remember that Verilog/VHDL code always executes in PARALLEL, since you're describing blocks of hardware.
Clarification (Score:3, Interesting)
A tutorial on Verilog [cmu.edu] is made available from a CMU professor. I think that Verilog will be more than sufficiently C-like to ease me into the PLD world.
I am aware of the huge difference of what kinds of behavior you are programming when you are using programmable logic devices vs. microcontrollers. But just because I am looking at a different paradigm doesn't mean it wouldn't be nice if some of my skills would transfer. I want to gain proficiency in PLD's because of the fact they can implement functionality otherwise requiring complex circuits. This is useful and I can't currently use it in my designs without another engineer to do the PLD.
I was really curious about the accessibility of the language. Java-like syntax would make it easier to entice more people to try to learn this skill, as Java is familiar to many people in the environments in which I work. I would bet Verilog has gained many adopters b/c of its similarity to C, who would otherwise use schematic entry to program PLD's, or avoid the parts altogether
To function well in the climate and level of embedded development today, you have to be able to do both sides of the equation if you want to be at all independent. I have seen horrific program design choices by people formally trained in EE, and I have seen atrocious, laughable circuits from those formally trained in CS.
A software guy sees a fault in a product and says it is a hardware problem.A hardware guy sees a fault in a product and says it is a software problem. The real engineer fixes the damn problem and tells the other two to grow up and pull their heads' out of their asses.
Re:Clarification (Score:1)
Perhaps its easier to learn, but as any programmable logic designer will tell you - it's also about synthesis and what comes after. I'll present to you the normal process flow of a programmable logic part (in this case, an FGPA):
1. VHDL or Verilog design
2. Synthesis through software tool (ie Synplicity, Leonardo, etc).
3. Synthesis results in a netlist
4. Place and Route, usually through vendor-specific tool (Xilinx, Aldec, Altera)
5. Place and route results in a device programming file (usually vendor specific, could be JEDEC format)
Of course, in between these steps are any number of required simulations. You will conduct many re-iterations of functional simulation and post-layout simulation of the design. As you will soon see, and has been mentioned previously, timing is one of the most essential things about a programmable logic design. If your timing is screwed up or your propogation delays too great, then your part is not going to work, and you're going to spend a lot of money in schedule slips and re-designs.
As has been said, there is a WHOLE LOT of details here that are not addressed by simply pointing to this JHDL tool and running with it. I've seen some of the main driving factors in FPGA and CPLD design are the tool--part interoperability and availability. JHDL is all nice and good - until you get to the point for synthesize and place and route (or fit for CPLDs) and discover you're SOL.
I recommend you first define your requirements (in detail), and develop a system level spec. At that point, if a programmable logic component fits the bill (FPGA or CPLD), then pick a language with good industry support (VHDL or Verilog) and move from there. In other words - reinforce success: both VHDL and Verilog have proven track records in the industry, and designers have had many successes using them.
Re:Clarification (Score:1)
I actually work for one of the large EDA vendors that sells a high-end ASIC synthesis and everything else solution. To me it appears that VHDL and Verilog will both stick around forever. I don't see anything else displacing them as HDL anytime within the next decade, since JHDL and SystemC has no advantage over VHDL or Verilog.
VHDL isn't the hardest thing to learn, either. The process is similiar to making a schematic- start with a library of pre-defined stuff, specify the external interface signals, define your internal state signals, form some groups of logic, and start to build the logic. Look, here's a 64 bit adder that adds every clock cycle:
LIBRARY ieee;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY adder IS PORT (
A : IN std_logic_vector(63 downto 0);
B : IN std_logic_vector(63 downto 0);
SUM : OUT std_logic_vector(63 downto 0);
clk : IN std_logic );
END adder ;
ARCHITECTURE rtl OF adder IS
SIGNAL OPERAND_A : std_logic_vector(63 downto 0);
SIGNAL OPERAND_B : std_logic_vector(63 downto 0);
BEGIN
ADDER_LOGIC : PROCESS (clk) BEGIN
IF (clk'event AND clk = '1') THEN
OPERAND_A <= A ;
OPERAND_B <= B ;
SUM <= OPERAND_A + OPERAND_B ;
END IF ;
END PROCESS ;
END rtl ;
You can build anything you want by sticking with the above framework. Don't worry about what kind of adder you have to build (CLA? CSUM?) Advanced synthesis tools decide that for you once you specify the clock frequency. The more advanced synthesis tools let you design even more complex logic (FIR filters, for example) quite easily as well.
Sad... (Score:1)
As a cmpe student at georgia tech, i encourage gte910h (name withheld) to take some REAL cmpe classes, ie more than ECE2030 which is probably where he was exposed to VHDL.
Take ECE2031, and while you're at it, maybe ECE2025. After that, you can take classes that really show off what VHDL can do, such as ECE3055 (Computer Architecture and Operating Systems)
some of these will be electives for you, but you might not get any credit at all for 3055.....it's still a fun class though.
My true advice: don't be such a wuss....if you want to be cmpe, switch to cmpe. we rock! join the dark side! (not only do we rock, we make more money too....)
--buddy
Re:Sad... (Score:1)
A EE degree to complement my CS degree might be a useful certification for industry, as well as provide additional training. There are many ways MaTech could have crossbred the CS and EE curriculum to make another major, but I don't really think a Computer Engineering degree is that useful, at least for any of my needs.
Re:Sad... (Score:1)
anyway, if you want to design hardware components, use a hardware description language that is standard in industry. the same goes for software
you don't see me writing programs in befunge, so why would you do hardware in something nonstandard?
if you don't want to make your own components, stay away from HDL.
--buddy
(btw, i'm just playing devils advocate mostly here..... so don't take it personally and look up gte160h..errr nevermind....)
Re:Sad... (Score:1)
I program a custom DSP, and let me tell you, the most useful classes I took in college (not GT)were my digital design classes. Programming comes pretty natural to me (as it does, I'm sure, for a lot of CS majors), but taking those classes widened my skillset quite a bit.
If I'm getting weird ass behavior out of my programs, I can grab the chip design and figure out WTF is going on (not HDL of any sort, our chip is schematically laid out in an ancient tool). If I need a new instruction in next chip, I have some idea of what is and isn't possible and can suggest ways of making it work. If I need to change the behavior on my dev board, I can grab the VHDL for the FPGA and change it. Very, very useful, allows me to get my programming done rather than waiting for other, extremely busy people to help me out.
So really, there's no reason for him to convert to the darkside. A CS with a decent digital hardware background is a good fit in the embedded world.
Tim
SystemC/JHDL vs. VHDL/Verilog (Score:1)
The short term reality is that the current toolset will probably take SystemC code and generated VHDL or Verilog for synthesis. Why? Because RTL synthesis tools are mature and VHDL and Verilog are mature. You are much better off learning VHDL and/or Verilog and developing the RTL in one of those. Just as in any other area of engineering, having a good foundation of knowledge is always better then learning a specific language/skill. (I'll call this the principle of first principles) If you're trying to hide a fundamental lack of knowledge of programmable logic and logic gates in general, you'll dig a hole for yourself. While not direct logic equations, VHDL or Verilog will keep you closer to the hardware.
As for SystemC vs. JHDL, my current opinion would be to go with something based on C. Why? Because it is far more likely that you'd write C code for the low-level software required by your system than Java. Also, I think JHDL as currently defined is meant as a straight-up replacement of VHDL/Verilog. I, personally, don't see a compelling advantage to use JHDL over VHDL or Verilog for standard RTL flows.
It appears JHDL is being positioned as a better solution for describing reconfigurable systems. It may offer advantages for that niche. However, I'd agrue that any higher level language (e.g. SystemC) would offer an advantage given a good JHDL/SystemC synthesis tool that understood reconfigurable devices. The synthesis tool should be able to implement reconfigurable logic based on your higher level description.
Chip design != Programming (Score:5, Informative)
Re:Chip design != Programming (Score:1)
I spent a lot of time doing synthesis and re-synthesis of modules and rewriting critical paths to meet constraints. Apparently, that's par for the course.
Before going to fabrication, we did extensive testing in simulation, and worked out almost all of the bugs then. When we got the first real chips, we ran through more testing and found three bugs, all of which we have software or hardware work-arounds for.
People are happy.
Think about your resume too... (Score:1)
Extremely Interesting Solution-Star Bridge Systems (Score:2)
I'm surprised I didn't see this at the top of the responses. These guys have, if their claims are accurrate (they are shipping hardware, supposedly to the likes of Nasa, so...), revolutionized both the FPGA development process and computer hardware architecture.
Their ideas seem to be based on the idea that a big array of FPGAs, which are reconfigured on the fly to suit a specific application at the gate level, is significantly (they claim orders of magnitude) faster than a conventional general purpose Von Neuman CPU or CPUs (even modern Athlons, etc). The frightening thing is that intuitively it makes sense to me, and if it really does work, it could change everything.
Obviously to make this work, they've developed a high-level language which compiles down to the FPGA level... They call it IIADL and/or Viva...
Looks fascinating.
-David
RISC CPU in JHDL (Score:2, Interesting)
See:
http://www.easystreet.com/~mbutts/xr16vx_jhdl.h
http://www.fpgacpu.org/log/jul01.html#010731
http://groups.yahoo.com/group/fpga-cpu/message/
Language Choice depends on the Designer (Score:1)
On the other hand, in chip design a language is used to express a model. In a proprietary language, the compiler errors will related directly to that model (like 'port not connected'), while with a mainstream software language you will see C++ or Java errors that might have nothing to do with a modeling error. So the answer to your question would be: if you are a hardware newbie, stick to an environment that supports you: VHDL, Verilog, or one of the new ones. If you like software engineering, go for C++ or Java.
AHDL seems like a very good choice (Score:1)
VHDL is obstuse looking cause its ADA.... (Score:1)
[Tangent] FPGA/PLD/etc starter kits? (Score:2)
I've been wanting to try using PLDs in some of my projects for pretty much as long as I've known such things existed,
but the cost of the tools I've seen is prohibitive to most anyone without corporate or university backing.
C-X C-S
Re:[Tangent] FPGA/PLD/etc starter kits? (Score:1)
According to their web page, it supports schematic entry, ABEL/HDLs.
http://www.xilinx.com/xlnx/xil_prodcat_landingp
Re:[Tangent] FPGA/PLD/etc starter kits? (Score:1)
The problem might be that the chips is developing rapidly so you might have to look a few years back in time to find something suitable to solder yourself compared to the new surface-mounted packages.
There are tools available for free, but it can be hard to grasp what you are getting and what you don't until you have worked with them.
Re:[Tangent] FPGA/PLD/etc starter kits? (Score:1)
But just from a quick search on Xilinx's store [xilinx.com], a JTAG connector and Prototype board runs about $550. The chips themselves can be pretty cheap (between $5 and $50), and they have stripped down toolkits available online [xilinx.com].
Re:[Tangent] FPGA/PLD/etc starter kits? (Score:2)
You can use Xilinx Webpack tools, available free from Xilinx [xilinx.com]. Supports both VHDL and Verilog. (I wish they had a native Linux version.)
With the XC2S200, you can fit a 32-bit RISC CPU, a bunch of peripherals, and a little memory all into the FPGA.
Thoughts From A Professional FPGA Developer (Score:2, Interesting)
First, VHDL was developed as a simulation language. Later, when industry discovered that what it really wanted was an automated tool that converted an HDL to a hardware design, VHDL was adopted as an input language for that process. Large portions of the VHDL language cannot, in fact, be used when the goal is to synthesize the resulting code into hardware. So, hardware development with VHDL is actually done with a subset of VHDL, typically referred to as synthesizable VHDL.
VHDL does indeed provide a higher-level approach to developing hardware. Some relatively simple language constructs can lead to a complex hardware implementation. It is, for instance, very easy to describe a state machine in VHDL and have the synthesis tool translate that state machine into gates and flip flops.
Since VHDL was not designed as a synthesis language, the translation of a VHDL construct into a hardware construct is not well defined. Each company that markets a VHDL synthesis tools approaches the problem differently. So, a given construct synthesized by one tool might lead to a well-optimized piece of hardware, while it leads to an ugly mess when synthesized by a different tool. To get reliable results, engineers that use synthesis tools must become experts in the particular synthesis tool they use.
Another disadvantage of VHDL is that it is very difficult to produce reusable code. It provides some mechanisms that seem useful for this purpose at first, but which, with experience, turn out to fall short. As a professional FPGA application developer, I've abandoned VHDL. I typically spend much too much time fighting with the language or the synthesis translation process.
So, what to use if not VHDL? The first thing that needs to be understood about JHDL is that it does not allow you to write your application in Java and then synthesize it into hardware. JHDL provides a mechanism for doing structural hardware design. So, you're not, for instance, writing a while loop in Java and having that translated into gates. What you would have to do is describe, in terms of the interconnection of the available hardware primitives and macros, the detailed hardware structure of your while loop. JHDL does not raise the accessibility of FPGA design. You still need to be a hardware engineer. You still need to understand the low-level nature of the hardware that you're building. What JHDL does is make it easier to do those things. JDHL is a Java-based library that allows you to build hardware structures using a real computing language.
Re:Thoughts From A Professional FPGA Developer (Score:1)
What do you currently use?? Verilog? CoreFire?
Re:Thoughts From A Professional FPGA Developer (Score:1)
Re:Thoughts From A Professional FPGA Developer (Score:1)
Re:Thoughts From A Professional FPGA Developer (Score:1)
While typical HDL's are designed to describe a fundamentally parallel process using procedural structures, CoreFire(tm) represents parallel structures as parallel structures using a data flow paradigm.
CoreFire(tm) provides a large body of ready-to-use cores that are optimized for speed on FPGA's. You don't need to understand anything about how to implement an FFT on an FPGA, all you need to do is route the data from wherever it is coming from to the core.
Where CoreFire(tm) truly shines, however, is in it's ability to create distributed control structures that are correct by construction. My experience with the development of FPGA applications is that building the computations is really the easy part. The hard part is getting the data into the system from the outside world, managing the data as it gets routed between various computations, and then getting it back out into the outside world. Typical HDL's encourage centralized control structures that have to be designed when you've got your computations all ready to go. With CoreFire(tm) you just draw out your computation as a dataflow graph and CoreFire(tm) produces the control that you need automatically.
JHDL + clock gating = quick, large, low power (Score:1)
Conservatism is good for you (Score:1)
My experience so far have made me into an old-schooler. Design is done simple and conservative. Things like:
(1) Whiteboards are good design tools. Use colors for datapath, control, exception/IRQ/flags, clocks etc.
(2) Design on whiteboard && paper == Simple code. As others have stated, a good thought out design doesn't require advanced language features. This in turn means less tool problems, faster toolruns etc.
(3) Learn the features of the language and their HW equivalents. Build test designs for different language constructs, guess the HW (including routing, registers and gates). Learn to see the HW when you write the code.
(4) Emacs + language mode == high productivity. Ignore managers that believe that Visual HDL, Renoir etc == good designs. (They don't).
Tools that give you the block hierarchy and possibly block interfaces with wires are very useful. But the actual contents should be written.
(5) Stick with Verilog. Ah! A language war you say. But there it really isn't. It's culture. EDA tools are just about always developed in the US. Americanos generally use Verilog, knows Verilog and are more comfortable with Verilog. This means that (A) The tools are developed for Verilog first and (B) generally have fewer bugs in the Verilog versions.
Superlog is a super language and I would love to use it - when it's at least as supported by the EDA vendors as VHDL. SystemC and other C-things? Look at the comments by colleguages in the ESNUG [deepchip.com] maillists. I wouldn't bet my design methodology on those languages and tools.
Platforms? NT was hailed as the new EDA platform, it went away. Linux is doing hefty inroads, they are everywhere at least as workstations for design entry, block simulation and synthesis jobs. Quite a few of the new tools are being developed on Linux and ported to Solaris (and HP-UX - the next OS to go in EDA?).
I have used VHDL and Verilog extensively. The ability to describe the HW is roughly the same in each of them. It's much more important to do a good arhitecture, partitioning and models. Learn that, pick up the language of choice and do lots of testruns. Good luck!
Using C++ to Simulate Designs (Score:1)
The gist of this is that the HDL world might be moving more towards C++ and away from Verilog due to the increase in simulation performance. The CRTL that we code is more like RTL (register transfer language) rather than abstracted/software-only C++, but it simulates 4-5 times faster on a 2GHz P4 (under Linux, hurrah) than Verilog. Plus, Verilog simulators that any reputable semiconductor-house will signoff with cost US$20k per license (or more).
Of course, the down side is that for now, we still have to run Perl scripts that translate the C++ to Verilog which is then synthesized using Synopsys (and simulated using VCS for sanity). But as things move forward, don't be surprised to see companies like Synopsys and groups like the IEEE moving to coming up with some way of writing RTL in C++ and synthesizing directly.
Re:Using C++ to Simulate Designs (Score:1)
Or C-Port/Motorola.
Prototyping sounds like a handy thing to do. There's a Quickturn spinoff that does something like that by putting some FPGA boards in a Sun workstation. But their entry price is something like US$700k as I recall. I can't remember the name of the company though.
As for the other environment issues - since I've just started there I can't give you specifics since I'm still learning the C++ RTL, let alone the big picture of the formal verification.
As for $20k for VCS, I'm not sure what our licencing terms are for it. But you're right, I'm sure it's quite a bit more than $20k now that I think about it. Given that Design Compiler is $100k a license why would VCS be much cheaper.
It's actually funny because three or four years ago I worked for a company that was being cheap so they bought one or two VCS licenses and six or so VCSi licenses. The difference: VCSi would put random wait delays of varying length in the simulation that merely slowed things down. And slow sims down it did. I used to see 45 minute delays in the middle of the sim. Rather annoying when it's 9:00pm at night and you want to go home but can't until the sim results come out. And for that we paid somewhere around $15-$20k. Such a deal!
View from an FPGA application engineer at Xilinx (Score:1)
I have a few words to say about the various methods.
Schematics: OK for 1000 gate designs, but it scales very poorly to million gate devices.
Verilog: Easy to learn, simulates fast, can be scaled to very large designs, but it lacks OOP features, as well as hooks for attributes to easily implement EDIF properties that are so important for low level FPGA floorplanning. Some tools have pragmas that will let you floorplan, but it's pretty crude, since pragmas don't have any language hooks for doing loops or anything. You pretty much have to extend Verilog with a macro processor like VPP before it becomes practical for million gate high level ASIC design.
VHDL: Complex language, takes a while to learn, has some good OOP features, as well as the all important attribute which permits structural design equivalent to schematic level implementation. VHDL is slow to simulate and VHDL also suffers from crappy parsers, since most synthesis vendors don't support the full language (Mentor comes closest). I can synthesize sin(x) and cos(x) with only a single tool (Leonardo) at this point, since it is the only tool which really supports floating point calculation during elaboration. Even then, I have to convert the float (type Real) into integers to realize actual hardware. Because of the poor language support, many designers are looking for System-C, Handel-C, or JHDL to give them the higher level synthesis support. Most new internal IP development at Xilinx these days is being done with VHDL, since Verilog is such a bitch to parameterize and floorplan. Believe it or don't, but a lot of IP cores in our Coregen tool are done in Java. (The Java code creates a structural netlist, with optional floorplanning.) This seems to be more difficult that VHDL, so it's losing popularity lately. SystemC, Handel-C, JHDL can sort of be lumped together as high level simulatable structural methods that all share one feature. They don't have the hooks for low level FPGA design (like attributes), so fancy stuff is pretty tough.
Bottom Line: All design methods will be tossed in the meat grinder of the marketplace and the best will survive. Come back in 5 years to see what happened.
JHDL (Score:1)
Re:stick with Verilog and VHDL (Score:1)
Regarding the Verilog versus VHDL war - I work in Silicon Valley and we tend to be very biased towards Verilog out here.