If you want hardware open to the transistor level and not just the microcode level, just use an FPGA. Actually FPGA is gate level, not transistor level but still is a lot closer than microcode.
The optimiser is largely irrelevant, as most optimisations are target independent these days. RISC-V support in GCC and LLVM is currently undergoing upstreaming, but it's a bit slow because the ABI has changed a couple of times. For a microcontroller it's probably fine: the privileged mode part of the spec is still not quite final, so I wouldn't recommend it yet for anything that you might want to run an OS on.
FPGA (Score:0)
If you want hardware open to the transistor level and not just the microcode level, just use an FPGA. Actually FPGA is gate level, not transistor level but still is a lot closer than microcode.
Re: (Score:4, Informative)
If you want hardware open to the transistor level and not just the microcode level ...
Like most RISC processors, RISC-V doesn't use microcode. Microcode is a CISC thing.
Re: (Score:2)
So, I was going to make a crack that it's a RISC instruction set, so there's not really that much to open, is there?
How's the compiler support - got a decent gcc optimizer for it yet?
Re:FPGA (Score:2)
The optimiser is largely irrelevant, as most optimisations are target independent these days. RISC-V support in GCC and LLVM is currently undergoing upstreaming, but it's a bit slow because the ABI has changed a couple of times. For a microcontroller it's probably fine: the privileged mode part of the spec is still not quite final, so I wouldn't recommend it yet for anything that you might want to run an OS on.