If you want hardware open to the transistor level and not just the microcode level, just use an FPGA. Actually FPGA is gate level, not transistor level but still is a lot closer than microcode.
RISC-V is an ISA only. It does not oblige implementations to follow any particular microarchitecture.
The religious wars between CISC and RISC were given up decades ago in favor of data-driven architectural decisions. If using sequenced uops solves the problem, they'll be used. For example, here the Cortex-A57 Software Optimization Guide explicitly refers to uops starting in section 2.1: http://infocenter.arm.com/help... [arm.com]
In the future there won't be any CISC or RISC, just wankers.
In particular, in the RISC-V case, the exact way of handling unaligned accesses is likely to vary a lot between implementations. In a microcontroller-class implementation, I'd expect it to handle these in microcode. For something particularly area-constrained, you might also implement multiplication and division in microcode.
"Spock, did you see the looks on their faces?"
"Yes, Captain, a sort of vacant contentment."
FPGA (Score:0)
If you want hardware open to the transistor level and not just the microcode level, just use an FPGA. Actually FPGA is gate level, not transistor level but still is a lot closer than microcode.
Re: (Score:4, Informative)
If you want hardware open to the transistor level and not just the microcode level ...
Like most RISC processors, RISC-V doesn't use microcode. Microcode is a CISC thing.
Re:FPGA (Score:2)
-1, misinformative
RISC-V is an ISA only. It does not oblige implementations to follow any particular microarchitecture.
The religious wars between CISC and RISC were given up decades ago in favor of data-driven architectural decisions. If using sequenced uops solves the problem, they'll be used. For example, here the Cortex-A57 Software Optimization Guide explicitly refers to uops starting in section 2.1: http://infocenter.arm.com/help... [arm.com]
In the future there won't be any CISC or RISC, just wankers.
Re: (Score:2)