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Intel Power

Research Shows RISC vs. CISC Doesn't Matter 161

Posted by timothy
from the just-a-couple-of-letters dept.
fsterman writes The power advantages brought by the RISC instruction sets used in Power and ARM chips is often pitted against the X86's efficiencies of scale. It's difficult to assess how much the difference between instruction sets matter because teasing out the theoretical efficiency of an ISA from the proficiency of a chip's design team, technical expertise of its manufacturer, and support for architecture-specific optimizations in compilers is nearly impossible . However, new research examining the performance of a variety of ARM, MIPS, and X86 processors gives weight to Intel's conclusion: the benefits of a given ISA to the power envelope of a chip are minute.
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Research Shows RISC vs. CISC Doesn't Matter

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  • by i kan reed (749298) on Thursday August 28, 2014 @09:10AM (#47773765) Homepage Journal

    Back when compilers weren't crazy optimized to their target instruction set, people coding things in assembler wanted CISC, and people using compilers wanted RISC.

    But nowadays almost no one still does the former, and the latter uses CISC chips a lot better.

    This is now a question for comp sci history, not engineers.

  • by Anonymous Coward on Thursday August 28, 2014 @09:36AM (#47773941)

    Yes. As noted by the study (That by the way isn't very good.) "When every transistor counts, then every instruction, clock cycle, memory access, and cache level must be carefully budgeted, and the simple design tenets of RISC become advantageous once again."
    Essentially meaning that "If you want as few transistors as possible it doesn't help to have the CISC to RISC translation layer in x86"

    They also claim things like "The report notes that in certain, extremely specific cases where die sizes must be 1-2mm2 or power consumption is specced to sub-milliwatt levels, RISC microcontrollers can still have an advantage over their CISC brethren." which clearly indicates that their idea of "embedded" systems is limited to smartphones.
    The cases where you have a battery that can't be recharged on daily basis is hardly an extremely specific case. Not that any CPU they tested is suitable for those applications anyway. They have essentially limited themselves to applications where "not as bad as P4" is acceptable.

  • by timeOday (582209) on Thursday August 28, 2014 @09:37AM (#47773951)
    Here is your answer [7-cpu.com], the A20 is freakishly slow compared to anything Intel would put their name on.

    Granted, you can build a tablet to do specific tasks (like decoding video codecs) around a really slow processor and some special-purpose DSPs. But perhaps the companies in that business aren't making enough profit to interest Intel.

  • by enriquevagu (1026480) on Thursday August 28, 2014 @11:27AM (#47775259)

    This is why we use the terms "Instruction Set Architecture" to define the interface to the (assembler) programmer, and "microarchitecture" to refer to the actual internal implementation. ISA is not bullshit, unless you confuse it with the internal microarchitecture.

  • by Rockoon (1252108) on Thursday August 28, 2014 @12:25PM (#47776135)

    No, the benefit of RISC is that you have many more on chip registers

    Nothing about RISC makes more registers inherent, and nothing about CISC makes less registers inherent. Now shut the fuck up and let the real nerds discuss.

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