Will 7nm and 5nm CPU Process Tech Really Happen? 142
An anonymous reader writes "This article provides a technical look at the challenges in scaling chip production ever downward in the semiconductor industry. Chips based on a 22nm process are running in consumer devices around the world, and 14nm development is well underway. But as we approach 10nm, 7nm, and 5nm, the low-hanging fruit disappears, and several fundamental components need huge technological advancement to be built. Quoting: "In the near term, the leading-edge chip roadmap looks clear. Chips based on today's finFETs and planar FDSOI technologies will scale to 10nm. Then, the gate starts losing control over the channel at 7nm, prompting the need for a new transistor architecture. ... The industry faces some manufacturing challenges beyond 10nm. The biggest hurdle is lithography. To reduce patterning costs, Imec's CMOS partners hope to insert extreme ultraviolet (EUV) lithography by 7nm. But EUV has missed several market windows and remains delayed, due to issues with the power source. ... By 7nm, the industry may require both EUV and multiple patterning. 'At 7nm, we need layers down to a pitch of about 21nm,' said Adam Brand, senior director of the Transistor Technology Group at Applied Materials. 'That's already below the pitch of EUV by itself. To do a layer like the fin at 21nm, it's going to take EUV plus double patterning to round out of the gate. So clearly, the future of the industry is a combination of these technologies.'"
Re:Car analogy? (Score:4, Interesting)
Everyone wants faster, cheaper, and lighter cars, but you cannae break the laws o' physics, captain.
That doesn't sound like breaking the laws of physics: making the car lighter will make it faster, as well as (assuming you avoid exotic materials) making it cheaper.
CMOS scaling limited by process variation (Score:5, Interesting)
There are a number of factors that affect the value of technology scaling. One major one is the increase in power density due to the end of supply and threshold voltage scaling. But one factor that some people miss is process variation (random dopant fluctuation, gate length and wire width variability, etc.).
Using some data from ITRS and some of my own extrapoliations from historical data, I tried to work out when process variation alone would make further scaling ineffective. Basically, when you scale down, you get a speed and power advantage (per gate), but process variation makes circuit delay less predictable, so we have to add a guard band. At what point will the decrease in average delay become equal to the increase in guard band?
It turns out to be at exactly 5nm. The “disappointing” aspect of this (for me) is that 5nm was already believed to be the end of CMOS scaling before I did the calculation. :)
Incidentally, if you multiply out the guard bands already applied for process variation, supply voltage variation, aging, and temperature variation, we find that for an Ivy Bridge processor, about 70% of the energy going in is “wasted” on guard bands. In other words, if we could eliminate those safety margins, the processor would use 1/3.5 as much energy for the same performance or run 2.5 times faster in the same power envelope. Of course, we can’t eliminate all of them, but some factors, like temperature, change so slowly that you can shrink the safety margin by making it dynamic.
Re:CMOS scaling limited by process variation (Score:2, Interesting)
Are you taking into account depletely-depleted MOS with controlled bias?
As I understand it, the Vt of the junction in present devices is controlled by the dopant level in the channel, and the source of Vt variation is from the shot noise in implantation. If you can increase the dopant concentration by 5x, you also decrease the variation due to shot noise by 5x. To compensate for the deeply depleted junction, you now need to add a body electrode to all the gates to bias them correctly, and a power supply tree for the biasing network. There is a silver lining, the Vt bias can be adjusted along with Vdd and clock frequency scaling so the device uses less power when idle.
I'm probably explaining it badly, here is the talk from Hot chips 24 [youtube.com] (third speaker).
-puddingpimp