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The Almighty Buck Hardware

Moore's Law Blowout Sale Is Ending, Says Broadcom CTO 267

Posted by samzenpus
from the paying-the-price dept.
itwbennett writes "Broadcom Chairman and CTO Henry Samueli has some bad news for you: Moore's Law isn't making chips cheaper anymore because it now requires complicated manufacturing techniques that are so expensive they cancel out the cost savings. Instead of getting more speed, less power consumption and lower cost with each generation, chip makers now have to choose two out of three, Samueli said. He pointed to new techniques such as High-K Metal Gate and FinFET, which have been used in recent years to achieve new so-called process nodes. The most advanced process node on the market, defined by the size of the features on a chip, is due to reach 14 nanometers next year. At levels like that, chip makers need more than traditional manufacturing techniques to achieve the high density, Samueli said. The more dense chips get, the more expensive it will be to make them, he said."
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Moore's Law Blowout Sale Is Ending, Says Broadcom CTO

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  • Right. (Score:0, Informative)

    by Anonymous Coward on Thursday December 05, 2013 @11:10PM (#45615527)

    The smell of bovine feces is palpable.

  • Process Node (Score:3, Informative)

    by spectral7 (2030164) on Thursday December 05, 2013 @11:24PM (#45615587)

    The most advanced process node on the market, defined by the size of the features on a chip, is due to reach 14 nanometers next year.

    Actually, the "process node" hasn't meant anything for years now [ieee.org].

  • by CaptBubba (696284) on Thursday December 05, 2013 @11:29PM (#45615627)

    350 may bring costs down, but it isn't a process node advancement and won't help cram more transistors per unit area into a chip.

    Instead it will just let them process more chips at once in most time-consuming processing steps such as deposition and oxide growth. The photolithographic systems, which are the most expensive equipment in the entire fab on a cost-per-wafer-processed-per-hour basis, gain somewhat due to less wafer exchanging, but the imaging is still done a few square cm at a time repeated in a step-and-scan manner a hundred times or more per wafer per step. Larger wafers however are posing one hell of a problem for maintaining film and etch uniformity, extremely important when you have transistor gate oxides on the order of a few atoms thick.

  • by SuricouRaven (1897204) on Friday December 06, 2013 @03:53AM (#45616735)

    The advancements in hardware were used to allow a saving in software development costs.

  • by Theovon (109752) on Friday December 06, 2013 @09:08AM (#45617719)

    It’s not about “green idiots.” It’s about the fact that chips will melt (burn? fry?) if you don’t keep them cool, and you can only dissipate so much heat from air cooling. Water cooling is used in HPC systems, but that too only goes so far. What’s next? Everyone needs a supply of liquid nitrogen to run their desktop PCs?

    The “power wall” is a real, practical problem, which we reached somewhere around 2001, where power dissipation hit ~150 Watts in high-end systems. And the challenges go beyond cooling. Did you know that half the pins (around 1000) on a modern CPU are used just for power and ground? Do the math on trying to get 150 Watts at 1 Volt through a single pair if wires.

    Oh, and what about mobile computers? Current battery technology can only old so much charge. Do you want your cell phone to get only an hour of useful life before recharging?

  • by jbolden (176878) on Friday December 06, 2013 @10:30AM (#45618259) Homepage

    They have. Functional programming. By explicitly avoiding side effects huge chunks of code can execute independently and in different orders. Moreover by organizing the code using functional looping constructors the parallel compilers can tell how to break things.

    Functional makes parallelism much easier.

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