The Mile Markers of Moore's Law Are Meaningless

szotz writes "Keeping up the pace of Moore's Law is hard, but you wouldn't know it from the way chipmakers name their technology. The semiconductor industry's names for chip generations (Intel's 22nm, TSMC's 28nm, etc) have very little to do with actual physical sizes, says IEEE Spectrum. And the disconnect is only getting bigger. For the first time, the "pay us to make your chip" foundries are offering a new process (with a smaller-sounding name) that will produce chips that are no denser than their forbears. The move is not a popular one."

Moore's law died already

[Anonymous Coward]

Anyone who actually works in the semiconductor industry could've told you this. (Ever notice how the GHz stopped growing a while ago? The move to multi-core happened around the same time and even that's stopped growing.) Yes, it's still possible to shrink transistors further but the speed and power reduction gains are diminishing and the costs of further shrinking are moving from merely eye-popping to astronomical.

Intel can afford to stay ahead of everyone else a bit (this is one of the primary reasons AMD is having difficulty staying alive) because of the huge volume that they have but even they're having problems.

Re:What's a mile?

[msauve]

It's one thousand (mille) paces of a Roman soldier, as modified through history. That seems to be as reasonable a basis for a unit of length as the meter, which is 1/10000000th the distance between the poles and the equator, as modified through history. Mileposts were markers placed by Roman roadbuilders as reference points.

Why do you ask - do you live in some backwards nation without a good educational system?

Re:What's a mile?

[Livius]

The Romans were counting the right and left steps as one pace.

Re:bad example

[Anonymous Coward]

To my knowledge, the node's name was based on the DRAM half pitch. But yeah, it's not that any longer. And in defense of GlobalFoundries, finFET does literally add an extra dimension to the calculation of FET geometries.

The node names are indeed based on DRAM half pitch, but CPUs haven't been made with the same process as DRAM since pitch was measured microns (eg. 0.13u).

The reality is that marketing CDs, including 32 and 22nm are only achieved through multiple patterning, and that won't change unless the industry adopts EUV or moves to a maskless process, neither of which is an economical proposition, given that the current best lightsource for EUV is a Tin vapor excimer laser, with a less than 1% dose/total energy efficiency. Part of the problem is EUV zoneplate mirrors have poor reflectivity compared to mirrors used with ArF excimer lightsources, and part of the problem is the low efficiency of the Tin vapor lasers. My prediction is that Stanford's solidstate FEL will be commercialised and used in place of excimer lasers. I'd like to see maskless litho (using DMR or DLP scanning) become a commercial reality, it will really change the market, as single dies will be manufacturable for nearly equivalent cost to volume production, but I wouldn't count on that happening too soon.

-puddingpimp