Intel Launches Core I7-4960X Flagship CPU

MojoKid writes "Low-power parts for hand-held devices may be all the rage right now, but today Intel is taking the wraps off a new high-end desktop processor with the official unveiling of its Ivy Bridge-E microarchitecture. The Core i7-4960X Extreme Edition processor is the flagship product in Intel's initial line-up of Ivy Bridge-E based CPUs. The chip is manufactured using Intel's 22nm process node and features roughly 1.86 billion transistors, with a die size of approximately 257mm square. That's about 410 million fewer transistors and a 41 percent smaller die than Intel's previous gen Sandy Bridge-E CPU. The Ivy Bridge-E microarchitecture features up to 6 active execution cores that can each process two threads simultaneously, for support of a total of 12 threads, and they're designed for Intel's LGA 2011 socket. Intel's Core i7-4960X Extreme Edition processor has a base clock frequency of 3.6GHz with a maximum Turbo frequency of 4GHz. It is easily the fastest desktop processor Intel has released to date when tasked with highly-threaded workloads or when its massive amount of cache comes into play in applications like 3D rendering, ray tracing, and gaming. However, assuming similar clock speeds, Intel's newer Haswell microarchitecture employed in the recently released Core i7-4770K (and other 4th Gen Core processors) offers somewhat better single-core performance."

Die size?

[msauve]

"a die size of approximately 257mm square."

I suspect that should be 257 square mm. A 257 mm square die couldn't even be covered by a standard sheet of paper (US:letter, EU:A4)

Boring on the Desktop Great in Servers

[CajunArson]

These chips are slightly faster (given equal core counts) than their predecessors but not in any interesting way.

  However, you have to remember that these are really server chips that are repurposed for high-end desktop use. The one vital metric where these chips shine is in their power consumption (or lack thereof): Techreport did a test where the 6-core 4960X running full-bore is using about the same amount of power as a desktop A10-6800K part ( http://techreport.com/review/25293/intel-core-i7-4960x-processor-reviewed/9 [techreport.com] )

That level of power efficiency will do wonders in the server world and these chips (and their 12-core bigger brothers) should do quite well in servers.

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Re:Boring on the Desktop Great in Servers

[JDG1980]

Intel segments the desktop and server market with ECC functionality. Xeons support ECC, everything else does *not*. So unless this new chip supports ECC, you're off your rocker thinking this is a repurposed server chip.

The same die is used for both chips; it's just that the ECC functionality is fused off in the non-Xeon parts binned for desktop use.

By the way, it's not strictly true that Xeons are the only Intel parts that support ECC. Ivy Bridge Celerons and Pentiums have this feature as well (if you use a compatible server motherboard). It was fused off on the mainstream desktop quad core parts because they wanted people to buy Xeon E3's instead.

Re:Another marginal perf iteration of Core

[Cajun Hell]

It's laughable how small the performance gains are between recent generations of Core processors. I realize there are other improvements like power consumption and integrated GPU performance but the desktop gamer isn't going to drop another grand to save watts or get better performance on an IGPU he never will use anyway.

The only thing that's laughable, is that the desktop gamer thinks everything is about him and that his concerns add up to even 1% of the market.

Re:wrong wrong wrong

[MrFlibbs]

Amazing. Everything you said about HT is completely wrong. Where ever did you get this information?

Intel's hyperthreading consists of two logical processors sharing the same compute resources. Each logical processor has its own register set but shares decoders, adders, shifters, cache, etc. as it goes about executing its assigned thread. The sharing process is vastly more complex and efficient than you seem to think -- there's no alternating of cycles. Once instructions are decoded into uops, they flow through the pipeline in a dynamic fashion that sometimes leads to one thread using most of the resources while the other one waits. In fact, this is a big advantage of the design -- when one thread stalls from a cache miss, the other one uses all the resources until the first thread's memory access completes. A much better plan than your scheme of using only even/odd cycles.

Managing this process is not simple, and steps must be taken to avoid both deadlocks and livelocks as the two threads compete for resources. But the process is dynamic -- the design allows one thread to run unimpeded when it makes sense to do so, while still preventing one thread from being starved at the other's expense. But this "every other cycle" notion of yours is pure nonsense. The core can retire up to four uops per cycle, and at times these all come from the same thread.

Re:Power consumption

[K. S. Kyosuke]

You're basically reiterating what I've said. The more you can compute with a fixed amount of energy, the less energy you consume for a fixed amount of computation.