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Oracle Unix Upgrades Hardware

Oracle's Sparc T5 Chip Evidently Pushed Back to 2013 98

Posted by timothy
from the when-visions-collide dept.
Mark Hachman writes in Slash Datacenter that the Sparc T5 chip Oracle announced earlier this year apparently won't be ready until sometime in 2013. John Fowler, executive vice president, Systems, Oracle, presented at Oracle Open World a chart outlining highlights of Oracle's plans for the future. "But Fowler also skipped over some bad news: an apparent delay for the Sparc T5. A year ago, Oracle’s Sun division announced the Sparc T4—and according to Fowler, Oracle chief Larry Ellison set a very high bar for the next iteration: double the performance while maintaining app compatibility on an annual basis. Apparently, that didn’t quite happen with the T5; Oracle had the opportunity to announce a T5-based server, and didn’t. That’s a bit of bad news for the Sun design team, which already had to watch Intel’s Xeon chief, Diane Bryant, give the preceding keynote. ... As detailed at this year’s Hot Chips conference, the T5 combines 16 CPU cores running at 3.6 GHz on a 28-nm manufacturing process. Continuing the trend of hardware acceleration of specific functions, Sun executives claimed the chip would lead in on-chip encryption acceleration, with support for asymmetric (public key) encryption, symmetric encryption, hashing up to SHA-512, plus a hardware random number generator."
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Oracle's Sparc T5 Chip Evidently Pushed Back to 2013

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  • Re:Oracle? SPARC? (Score:4, Insightful)

    by fm6 (162816) on Thursday October 04, 2012 @06:50PM (#41553895) Homepage Journal

    Glacial indeed, if they haven't already done it. Like the other 99% of the industry.

    One has to be really dense not to see this trend. ALPHA is gone. MIPS is only used in embedded devices. Itanium and POWER are strictly legacy products. And yet people still believe that SPARC can survive in the server space.

    I'd be sad too if I still worked at Sun. But not only does the failure of this product line no longer affect me, even abandoning SPARC completely would not save it. Computers are Dead [slashdot.org].

  • Re:Sparc T5! (Score:3, Insightful)

    by Snorbert Xangox (10583) on Thursday October 04, 2012 @10:32PM (#41555127)

    "If you were plowing a field, which would you rather use: Two strong oxen or 1024 chickens?" - Seymour Cray.

    The devil is in the details. SPARC has lots of registers, very true. But it needs more user-accessible registers, because its address modes are simpler, and you need to do more address computations in registers. Register windows were like a fully associative cache for a few levels of your call stack... but then you have to save more stuff when you do a context switch, and I suspect they were part of why Sun was late to doing full out-of-order execution in their SPARC implementations.

    I was a big fan of the early RISC chips, because that architectural style was bringing forth implementations which got much better bang per CPU transistor than other commercial chips at the time. That lead was eroded seriously by Intel with the Pentium Pro - certainly in terms of bang per buck - which was embarrassing for people who wanted to point out some inherent "elegance" or other timeless quality of RISC that was its great advantage. Whatever that counted for, Intel's designs and better process technology could more or less match with ugly old x86.

    The time when you could play Top Trumps [wikipedia.org] with computer architecture specs is really over. Decisions that were clear winners at a particular time, in terms of process technology, memory bandwidths, and compiler quality, can turn out not to be as optimal when the market, or what is cost-effective to produce, changes over time.

    The T series SPARC chips came out of work done by Kunle Olukotun at Afara Websystems and then brought in-house by Sun. They represented a great point-in-time improvement for high parallelism, cache-unfriendly, integer server loads over what was under development inside Sun at the same time, especially when cost and power were taken into account. Some of those decisions in the T1 got revised for the T2 - one FPU for the whole chip turned into one FPU per core, for instance - but the per-die core count got halved for the T4, so again the Top Trumps viewpoint doesn't really illustrate whether one processor is better than another.

    Bottom line is, does it run the stuff you want to run, for a good TCO?

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