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Mass Production of 450mm Wafers Bumped Back Again: 2018 67

Posted by Unknown Lamer
from the shiny-discs-from-the-future dept.
Taco Cowboy writes with news on the slipping schedules in the move toward both larger wafers and 3D integrated circuits in the semiconductor fab world. From the articles: "TSMC ... said it planned to start mass-producing next-generation 450mm wafers using advanced 10-nanometer technology in 2018. The advanced 10-nanometer chips could first be used in mobile devices and other consumer electronics, like game consoles, that demand high-performance and low power consumption. The plan was included in the latest technology roadmap unveiled by TSMC about one year after the chipmaker attributed its delay in making 450mm wafers, originally scheduled in 2015, to semiconductor equipment suppliers' postponement in developing advanced equipment for manufacturing amid the industrial slump. Chipmakers can get 2.5 times more chips from a 450mm wafer than from a 300mm wafer ... The industry's gradual migration toward 3D ICs with through-silicon vias (TSV) is unlikely to happen until 2015 or 2016, according to sources at semiconductor companies. Volume production of 3D ICs was previously estimated to take place in 2014. Leading foundries and backend assembly and test service companies have all devoted much of their R&D efforts to TSV development, and are making progress. The major players are believed to be capable of supporting 3D ICs by 2014, but the emerging technology going into commercial production may not take place until around the 2015-16 timeframe." Probably one of the most interesting presentations at HOPE9, "Indistinguishable From Magic: Manufacturing Modern Computer Chips," covered modern semiconductor fabrication and why these things are cool. If you're interested in more background (what do all of those TLAs mean?), check out the slides / audio (or attached video of the presentation from YouTube).

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Mass Production of 450mm Wafers Bumped Back Again: 2018

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  • by MozeeToby (1163751) on Wednesday September 05, 2012 @11:31AM (#41235197)

    Um, no. Larger wafers are a cost savings measure. 450mm means that you end up with fewer incomplete chips on the edges of your wafer, which in turn increases your yield. No one is stamping out a single CPU on a 450mm wafer.

  • by tlhIngan (30335) <(ten.frow) (ta) (todhsals)> on Wednesday September 05, 2012 @12:38PM (#41236151)

    current wafers still yield large numbers of current-sized chips. and for the most part, chip architects are not primarily limited by available area: relentless process shrinks bring, if anything, more transistors than they know how to use. sure, you can always throw on more cache, especially L3. but the main issues today are power and IPC/TLP-type efficiency, not space. the K20 team at NVidia might disagree, but they _should_ be pushing the bounds, since their target is less cost-sensitive HPC, not commodity/gaming.

    in short, the action is in litho, process, transistor topology, power and microarchitecture, not the number of chips spoiled by the edges.

    That's correct for transistor-limited (aka pin-limited) chips, but not so for area-limited chips.

    Yes, just like we have CPU-bound software and IO-bound software, we have area-limited and pin-limited chips. Pin-limited chips are where the I/O balls are keeping chips from becoming bigger - you see this as CPUs, SoCs, chipsets and other utility chips (many bus architectures are redesigned to be more conservative on their pin usage - why consume 64 pins when you can use 16).

    Area limited chips are where the actual silicon area limits their usage - too big and flaws mean lower yields, too small and your devices may not meet requirements. These kind of devices are typically memory devices - the storage array is the largest consumer of area (the logic fits neatly around it) and the larger you can make the storage array, the bigger the memory.

    Memory devices are also some of the most dense, transistor wise (a CPU has tons of "random logic" that means wiring is what keeps transistors spread apart, not transistor density). For a given process node, if you can double the area of the storage array, you double the storage.

    And memory devices cover a wide gamut - from imaging devices (CCDs, CMOS), standard DRAMs and SRAMs, and EEPROM-style memory (including flash memory).

    Basically the amount of storage you can stick is limited by area (double area, double storage, eseentially), but if you make the area too big, yields go down as the impact of an imperfection destorys the entire chip.

    A larger wafer has more area available, and since wafer costs are mostly fixed (a single wafer costs anywhere from $1000-3000 or so), the number of good chips has to pay for it all. The more good chips (higher yield), the cheaper the cost.

    A larger wafer means more chips can be made, so cheaper overall memory devices - which translate to cheaper SSDs, cheaper DRAMs, digital cameras with larger sensors, dSLRs with full-frame sensors at a budget price (this one especially - the sensor is the most expensive part because it's genuinely a HUGE piece of silicon and only a handful make it out of a wafer, even allowing for bad pixels).

    For other chips, a larger area does allow for more wiring, which is what dominates chip design, not transistors. If you take something like an FPGA - the thing limiting it IS area - wiring area is extremely limited.

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