IBM Mainframe Running World's Fastest Commercial Processor 158
dcblogs writes "IBM's new mainframe includes a 5.5-GHz processor, which may be the world's fastest commercial processor, say analysts. This new system, the zEnterprise EC12, can also support more than 6-TB of flash memory to help speed data processing. The latest chip has six cores, up from four in the prior generation two years ago. But Jeff Frey, the CTO of the System Z platform, says they aren't trading off single-thread performance in the mainframe with the additional cores. There are still many customers who have applications that execute processes serially, such as batch applications, he said. This latest chip was produced at 32 nanometers, versus 45 nanometers in the earlier system. This smaller size allows more cache on the chip, in this case 33% more Level-2 cache. The system has doubled the L3 and L4 cache over the prior generation."
Re:CPU (Score:5, Informative)
Re:Memory performance? (Score:5, Informative)
CPUs have not accessed main memory synchronously in decades. There are many hundreds of cycles lost if the processor stalls on a RAM access, not just from the length of the wiring but the addressing logic too. In fact, modern CPUs don't do word-level access to RAM, but rather pull in whole cache lines in a more packetized memory access protocol. Even in a multi-CPU SMP system, they don't actually communicate through system RAM anymore, but rather communicate CPU-to-CPU with a cache coherency protocol that provides the illusion of a shared system RAM. Each CPU really has its own set of local RAM behind its own cache and on-chip memory controller.
Even the L2 or L3 caches are unable to keep up with the CPU, but they are still significantly faster than system RAM, so they still help when the working set can fit there.
Re:Reading the words "new mainframe" (Score:4, Informative)
Mainframes run a surprising amount of critical workloads in the real world. They're vastly different than open systems, but they can be kept running through almost anything, if you're willing to spend enough money.
Re:bogus claims (Score:4, Informative)
They claimed "faster", not "more powerful"; clock frequency is the only thing they need to reference for that claim.
Re:bogus claims (Score:5, Informative)
Re:L4 cache (Score:5, Informative)
Except.... (Score:2, Informative)
Except the 5.5GHz may not be all that fast, as the Z-line of CPUs are the old IBM 360 instruction set, which is is so large, complex, and baroque that it is mostly usually implemented through a thick layer of microcode.
So 5.5GHz may be the speed of the microcode level, the actual "machine instructions" may be a considerable sub-multiple of that.
Re:Memory performance? (Score:4, Informative)
These chips make up for the high latencies by having many instructions being executed simultaneously, so if one dependency chain completely stalls out on a cache miss any other dependency chains can still fill up the execution units keeping the processor just as busy as if there were no stall at all until everything left in the pipeline is dependent on the result of the stalled out operation.
Re:CPU (Score:3, Informative)
Re:No the basic Core i& extreme will smoke it (Score:5, Informative)
Re:Except.... (Score:5, Informative)
No, that's not a correct supposition -- quite the opposite, actually. All processors, including Intel X86, use microcode (or what IBM calls millicode) to a degree.
At least from what I've read about the past few generations of S/3x0 chips, millicode is more like PALcode on the Alpha processor than like traditional microcode, i.e. it's a combination of regular machine code and processor-specific instructions that access specialized registers etc., running in a special processor mode with (presumably) fast entry and exit, support for said processor-specific instructions (which presumably trap in either both "problem state", i.e. user mode, and "supervisor state", i.e. kernel mode), and its own bank of general-purpose registers (part of the "fast entry and exit"). Instructions implemented in millicode trap to millicode routines that implement them.
What IBM called "microcode" rather than "millicode" was implemented using processor-specific instructions completely different from the machine's instruction set (instructions often having fields that directly controlled gates).
(And then there's System/38 and the pre-PowerPC AS/400, where the processor instruction set was a CISC instruction set implemented using microcode, and where the compilers available to customers generated code in an extremely CISCy instruction set [ibm.com] that the low levels of the OS translated into machine code and ran. For legal reasons - they didn't want to have to be required to make the low-level OS code available to "plug-compatible manufacturers", i.e. cloners - they not only called the microcode that implemented the processor instruction set "microcode" ("horizontal microcode", as it probably was "fields directly control gates"-style horizontal microcode), they also called the aforementioned low level OS code "microcode" as well, even though it ran from main memory and its instruction set was the instruction set that was actually executed in application code ("vertical microcode"), and had the group working on that code report to a manager in the hardware group. See Frank Soltis's Inside the AS/400.)
IBM knows it well. After all, they invented microcode/millicode in the System/360 in 1965.
"Invented", no; the paper generally considered to have introduced the concept was "Microprogramming and the Design of the Control Circuits in an Electronic Digital Computer" [microsoft.com], by Maurice Wilkes and J. B. Stringer, from 1953. S/360 may have been the first line of computers to use microcode in most of the processors (S/360 Model 75 was, I think, implemented completely in hardwired logic).
Very cutting edge -- so cutting edge I've got to crack open some engineering manuals to try to figure out what they've done, although they probably need to write those manuals.
Well, for the previous generation, there's Volume 56, Issue 1.2 of the IBM Journal of Research and Development [ieee.org] has some papers on the z196, but, alas, not for free online. They may publish an issue on the zEC12 at some point.
Re:Reading the words "new mainframe" (Score:4, Informative)
It may not be just you. But I think a lot of people really have no idea of just how many mainframes are still chugging away doing what they've always done.
My wife does outsourced SAN storage, and they still have a couple of clients with big iron running.
Every couple of years when everybody has forgotten about the machines, an IBM tech will call up and say that the machine has phoned home and has a part that needs to be swapped out and that he needs to go onsite. Which usually leads to several hours of people trying to remember what it is and where it is (except the guys who work in the data center, who can't miss it).
I've worked in several places that have had mainframes for literally decades. And I've even worked on a project or two which tried to replace ancient, purpose built software with some shiny new stuff. In the cases I've seen, after spending a few years a a few million dollars ... they still can't replace the mainframe and scrap the project.
I knew someone in the early 2000's who had retired from his job with a full pension, and was back as a consultant making at least 3x his old salary because they no longer could find someone who knew the machines and the software like he did.
Mainframes haven't gone away. Not by any stretch. And I bet this one still runs the stuff from the IBM 360 days quite nicely.
Re:CPU (Score:5, Informative)
L3 is 48MB, (see p. 43) [ibm.com], not GB as The Register had it, thanks for noticing that.
Re:Thanks, I've already found some Benchmarks (Score:5, Informative)
OK, let's put some of this stupidity to rest.
First, nobody who knows anything uses MIPS to compare perfomance between two different architectures. MIPS is only marginally useful in the best of conditions, and even then is only useful as a relative measure between two machines of the same architecture running the same workload.
Second, Core i7 servers execute 178 BILLION instructions every second, on average? Seriously? 80 instructions per clock cycle, sustained? Bullshit.
Third, your nice shiny rack of Core i7 servers doesn't mean anything if it can't run your software.
Fourth, the actual performance of a Z114 processor is around 780 MIPS, not 26. So why do they have that 26 MIPS 'dialed down' model? Because some customer asked for it. Why would a customer pay $800K for a 780 MIPS machine when he only has 26 MIPS of workload? Why would the customer pay software licensing fees for a 780 MIPS machine when he only has 26 MIPS of workload?
Fifth, 'your experience' with IBM mainframes is non-existant, or you wouldn't be making these stupid mistakes and claims.
Re:Thanks, I've already found some Benchmarks (Score:3, Informative)
CPU isn't the single item with mainframes. Mainframes tend to have large I/O buses, and that is something that tends to be forgotten about when people talk about CPU power.
Mainframes are designed to do business tasks, be it CICS operations, DB2 transactions, or other integer based operations that require tons of data going in and tons of data going out at a time. This is why IBM has such a good caching design. Having the ability to get the numbers into and out of the CPUs is what mainframes are designed to do.
If someone expects top notch floating point operations, expect to be disappointed. MIPS and sheer bus bandwidth rule the roost when it comes to this section of computing.
Re:bogus claims (Score:5, Informative)
IBM gets the speed because cost is no option. Here is how they do it.
1. Low yield. These chips have a very large die size so the yield is going to be lower but the price is high so the trade off works.
2. Binning. The slower chips will go into the lower end machines that use the Z114.
3. Multi chip modules again to allow careful selection and improved yields.
4. Crazy levels of cooling. These have the very best cooling they can fit.
5. Professional operators, maintenance, and construction. The entire machine will be built like an expensive watch from the cooling to the memory system. The operators will follow all the procedures and if something is not perfect they will call IBM to send out a tech if the computer didn't do it.
Other companies know how IBM does this they just do not have the resources in place to compete with IBM in this market. Instead they go for the easier lower hanging fruit.
Too bad IBM blew it with the PC. If they had not been under extreme anti-trust pressure and had faith that PC where going to take off they could have used a 16 bit version of the System 360 ISA for the CPU maybe based on the 360/20 or maybe the 22.