SSD Latency, Error Rates May Spell Bleak Future 292
Lucas123 writes "A new study by the University of California and Microsoft shows that NAND flash memory experiences significant performance degradation as die sizes shrink in size. Over the next dozen years latency will double as the circuitry size shrinks from 25 nanometers today, to 6.5nm, the research showed. Speaking at the Usenix Conference on File and Storage Technologies in San Jose this week, Laura Grupp, a graduate student at the University of California, said tests of 45 different types of NAND flash chips from six vendors using 72nm to 25nm lithography techniques showed performance degraded across the board and error rates increased as die sizes shrunk. Triple-Level NAND performed the worst, followed by Multi-Level Cell NAND and Single-Level Cell. The researchers said MLC NAND-based SSDs won't be able to go beyond 4TB and TLC-based SSDs won't be able to scale past 16TB because of the performance degradation, so it appears the end of the road for SSDs will be 2024."
I want HAL's memory (Score:4, Interesting)
Re:Sounds legit (Score:5, Interesting)
We already have the breakthrough, but it's not Flash, it's PRAM [wikipedia.org].
Re:Sounds legit (Score:5, Interesting)
Perhaps it's already been found:
http://en.wikipedia.org/wiki/Phase-change_memory [wikipedia.org]
PCM still has hurdles to overcome, but it's generally considered that performance increases as size decreases, the opposite of NAND.
Re:Sounds legit (Score:4, Interesting)
Didn't you hear? We've reached the limitations of technology and innovation.
That's why it's so stupid to put any money into non-fossil energy. If we can't power a house by solar energy now, we'll never be able to and we just have to accept it.
It's the End of History. Again.
Several fundamental flaws in their assumptions (Score:4, Interesting)
While they discuss individual SSDs, modern flash storage arrays ( http://www.violin-memory.com/products/6000-flash-memory-array/ [violin-memory.com] ) can hide all the write latency and its effects on read latency. When you start talking about 16TB SSDs the same techniques can be used.
As far as bandwidth and IOPs, they use a 4K/8K write size for MLC/TLC, but MLC already exists with 8K pages, as well as having the ability to write more than one plane at once, which doubles the write bandwidth. Double the page size again and you double the BW.
Now bigger page sizes only help on the reads if you can use more than a single user read worth of data in the page, which might be possible depending on what the system knows about access patterns. But without making assumptions about the ability to store data together that's likely to be read together, garbage collection, which can wide up reading more bytes than the user does, can use most of the data in a page.
So there are factors of 2X, 4X maybe 8X in performance that the paper misses out on.
As far as density, it is not necessary to go to smaller features to get more bits per chip by using 3D techniques such as Toshiba's P-BiCS (Pipe-shaped Bit Cost Scalable) MLC NAND which allow vertical stacking which increases density without using smaller features with their worse performance and lifetime.
The group at UCSD that authored this has done some nice work so I don't mean to be too negative, but they are trying to predict too far from a limited and faulty set of assumptions which unfortunately negates much of the validity of this paper.
jon
p.s. in the interests of full disclosure, I make the arrays in the first link :)
Re:Sounds legit (Score:5, Interesting)
They all have much lower densities. The highest is PRAM at 1 Gbit with a 58 nm process, demonstrated by Samsung in February 2011. That's way too low.