The Transistor Wars 120
An anonymous reader writes "This article has an interesting round-up of how chipmakers are handling the dwindling returns of pursuing Moore's Law. Intel's about four years ahead of the rest of the semiconductor industry with its new 3D transistors. But not everyone's convinced 3D is the answer. 'There's a simple reason everyone's contemplating a redesign: The smaller you make a CMOS transistor, the more current it leaks when it's switched off. This leakage arises from the device's geometry. A standard CMOS transistor has four parts: a source, a drain, a channel that connects the two, and a gate on top to control the channel. When the gate is turned on, it creates a conductive path that allows electrons or holes to move from the source to the drain. When the gate is switched off, this conductive path is supposed to disappear. But as engineers have shrunk the distance between the source and drain, the gate's control over the transistor channel has gotten weaker. Current sneaks through the part of the channel that's farthest from the gate and also through the underlying silicon substrate. The only way to cut down on leaks is to find a way to remove all that excess silicon.'"
Intel's 3g gate transistors stop all current (Score:5, Insightful)
Current sneaks through the part of the channel that's farthest from the gate and also through the underlying silicon substrate
big "huh" at this article excerpt, the point of Intel's 3d gate transistors is it allows for a fully depleted region of silicon in the channel. IE, the gate is so close to the silicon, NO electrons exist in the channel when it is off. The only leakage current you can have then through the channel is quantum tunneling, and that's basically nil; bringing the total current consumption of the transistor down by a factor of 10. Ho hum silly slashdot summary, get off my lawn!