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Oracle Sun Microsystems Hardware

Oracle Demos New SPARC T4 Processor 127

Posted by timothy
from the store-away-from-volatile-gases dept.
MojoKid writes "Oracle is publicly demonstrating its new T4 processor today and is shipping beta test systems to selected partners. The new T4 chip is a major departure from previous designs. The T4 offers a maximum of eight cores per physical chip and keeps the T3's eight-threads-per-core limitation. The T4 compensates for its lower maximum theoretical throughput in several ways. First, the T4 is an out-of-order processor with an enhanced branch predictor. Its maximum speed is said to be at least 3GHz, nearly double that of the 1.67GHz T3. Oracle claims the chip's single-threaded performance has been significantly boosted, and expects T4 to deliver a 2x-7x speed increase in single-threaded workloads compared to T3."
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Oracle Demos New SPARC T4 Processor

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  • by Anonymous Coward on Tuesday September 27, 2011 @09:12AM (#37525470)

    Is it me, or did Oracle completely miss the point of SPARC? We used to use SPARCs where I work for huge, multi-thread or child-spawning applications. If you want a number cruncher, go somewhere else. Go buy a POWER CPU. SPARC's shining glory is the massively threaded model where you spawn tons of little instances of the same thing that serve a quick, non-intensive purpose and die. Once again, Oracle is taking something they bought and trying to ram the square object into the round hole they call their business model.

    Interestingly enough, the captcha for this was "idiots"

  • by angel'o'sphere (80593) on Tuesday September 27, 2011 @10:01AM (#37525940) Homepage Journal

    # prstat
    Total: 341 processes, 9909 lwps, load averages: 20.86, 19.36, 20.41

    # prtdiag -v
    System Configuration: Sun Microsystems sun4u SPARC Enterprise M9000 Server
    System clock frequency: 960 MHz
    Memory size: 262144 Megabytes

    Only roughly 3 processes per core ... and yes that is 262 GIGA BYTES of Ram. How much again can an ARM address?

    Well, keep in mind: when we talk about SPARC or the Power PC architecture we also talk about memory bandwidth, failover safety, attached I/O devices etc.

    I don't see anyone trying to build "big iron" with ARMs right now.

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