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IBM Hardware Technology

IBM, 3M Team To Glue Together Silicon "Bricks" 81

Posted by samzenpus
from the stack-your-chips dept.
coondoggie writes "IBM and 3M today said they will jointly develop a new line of adhesives they hope will let them make it possible to build commercial microprocessors composed of layers of up to 100 separate chips. Such stacking would allow for higher-powered servers and more advanced consumer electronics applications, the companies stated. Processors could be tightly packed with memory and networking, for example, into a 'brick' of silicon that would create a computer chip 1,000 times faster than today's fastest microprocessor enabling more powerful smartphones, tablets, computers and gaming devices."
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IBM, 3M Team To Glue Together Silicon "Bricks"

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  • Hmmm
  • So... (Score:4, Insightful)

    by Ibiwan (763664) on Wednesday September 07, 2011 @06:25PM (#37334288) Journal
    Stacking these things is all well and good, but at what point do heat considerations become a primary concern? Lately I haven't gotten the impression that volume of ICs is our biggest bottleneck.
    • Stacking these things is all well and good, but at what point do heat considerations become a primary concern? Lately I haven't gotten the impression that volume of ICs is our biggest bottleneck.

      The article indicates that heat is already a primary concern. 3M's role in the endeavor is to develop adhesives with good thermal conductivity.

      • If they're finally starting to build up then they will probably need to start looking at ways to transport heat out the sides as well as the top of the die. I wonder if they'll be able to reduce the power requirements though by creating shorter "vertical" paths to the next plane instead of making so many longer cross-die journeys.
    • Stacking these things is all well and good, but at what point do heat considerations become a primary concern? Lately I haven't gotten the impression that volume of ICs is our biggest bottleneck.

      Eventually the 'bricks' will end up with shapes that has the best heat transfer properties, e.g. a 'ring' shaped cpu dipped in cooling liquid.

      • by jamiesan (715069)
        Then they can just peel the top one off and stick it to the monitor if it gets too hot right?
    • 1) "Standard" solution is to interleave copper fins between chiplets to take heat out -- and yes, it has been major problem for 3D integration.

      2) Of course it's Intel and 3M, but do not think that this is new at all -- at my previous place of employment (6 years ago) we have been working with these guys: http://www.irvine-sensors.com/r_and_d.html#Neo-Stack [irvine-sensors.com] -- and they have this technology for quite some time before that.

      Interesting tidbit I've heard from their CTO (I think): if you take a full height rack

    • by kheldan (1460303)
      Ironically enough I'm reading an old science fiction trilogy from the 80's featuring a race of aliens whose technology is remarkably similar to this. Them embedded heat-pipes in the layers to conduct heat away. Why can't they do something similar here?
    • How about we stack RAM chips - lower latency would improve throughput without much heat.
    • by mwvdlee (775178)

      I think part of that problem can be solved simply by making pathways a lot shorter.
      Volume of IC's isn't so much the bottleneck as it is the result of another bottleneck; the inability to cross pathways in a single layer.

    • by ultranova (717540)

      Maybe the stack could simply include channels for cooling liquid?

    • by tlhIngan (30335)

      Stacking these things is all well and good, but at what point do heat considerations become a primary concern? Lately I haven't gotten the impression that volume of ICs is our biggest bottleneck.

      If you're using low-power efficient processors like ARMs, heat isn't really a huge issue - even going full tilt a typical SoC would draw 2.5W or so tops. Basically, passive cooling without a heatsink is more than adequate.

      Stacking the memory and flash on top of the chip (commonly done today with multi-chip packaging

  • That is going to be fun to cool...

    I wouldn't be surprised if there are some specialty niche application guys who are just drooling at the prospect of vastly increased silicon area without more board space or interconnect hassle; but anybody who is cranking the clock, the power handling, or both, is going to find the utility of the layers at the center a bit dubious.
    • by drinkypoo (153816)

      Didn't we JUST see an article about unimolecular pumps? If they put some grooves in the silicon layers they can just use on-die liquid cooling. ;)

  • 100 more ways to brick a machine.
  • I'm sure I'm one of thousands of folks thinking that how to glue together chips must be the least concern, and how to dissipate heat must be the highest?

    The only thing I can think of that makes the adhesive important would be how well it holds up under heat, so maybe thats why its hard to do?

    I imagine such a "brick" of silicon would probably have to have active cooling build into it, such as etched-in heat pipes or even some kind of micro fluid cooling system. Thats where the interesting stuff is happening

    • by Surt (22457)

      The announcement says that the glue itself will be heat dissipating. That's pretty much the focus of the whole project.

      • by greywire (78262)

        And, what, you expected me to READ the article first? Pshaw! This isn't the slashdot I know and love if you actually expect me to read the article and be informed first...

        • by Surt (22457)

          Not at all! After all, what purpose do the comments serve if not to clarify the summary for all who skipped reading the article?

    • by sehlat (180760)

      I mean, really.. glue.. how exciting is that?

      No product on any scale from chips to countries is good unless the infrastructure supports it properly. Glue is "infrastructure," not sexy, but utterly vital. A glue that permits building a Borg Cube in microchip form will permit the firm with the technology to say "Resistance is futile." and mean it.

      • Good point. As I recall, the fundamental advantages that Seymour Cray introduced with the Cray supercomputers were primarily about infrastructure - cooling the boards and chips, and using interconnect wiring that was all the 'exact' right length for the high speed signals. Since the wires were the same length, the propagation delay between boards could be accommodated in the logic on each board, so the individual processors could act in parallel increasing the overall clock speed. (I know this could be s

    • by perpenso (1613749)

      I'm sure I'm one of thousands of folks thinking that how to glue together chips must be the least concern, and how to dissipate heat must be the highest? The only thing I can think of that makes the adhesive important would be how well it holds up under heat, so maybe thats why its hard to do?

      You are correct that thousands are thinking about heat dissipation, it particular the folks at 3M who are working on this project are thinking about that. The article indicates that their primary role is to develop adhesives with the necessary heat dissipation.

  • Three possibilities:

    1) Moore's Law broken

    2) This won't see the light of day for a LONG time

    C) They are exaggerating.
    • by Surt (22457)

      It's #2. This isn't something they've built, it's something they're aiming to build. Perhaps they have good reason to believe they'll succeed, but that doesn't change the fact that this is a vaporware initiative announcement.

    • by ArsonSmith (13997)

      Or Moore's law will continue due exactly to this with doubling every 18 months until they hit the 1000x improvement where they will then have to look to other tech approaches to continue keeping up with Moore's law.

    • If I understand correctly, Moore's law should hold out for another 4 years - that is we have mapped out the technology to get to chips down to 11 nanometers - it just a matter of implementing that technology - which is no small feat. After that - what?

      3d chips - by gluing chips on top of each other
      3d chips with different strata
      quantum bits
      quantum tunneling to replace current gates
      etc.

      If Moore's law is to continue, some new rabbits are going to have to pulled out of hats. Maybe this?

      • by Surt (22457)

        Moore's law is ending in most of our lifetimes. When, exactly, is somewhat unclear, but the horizon is less than 40 years, at which point our single-atom transistors will be so numerous they will occupy the volume of our houses.

        • by macshit (157376)

          Moore's law is ending in most of our lifetimes. When, exactly, is somewhat unclear, but the horizon is less than 40 years, at which point our single-atom transistors will be so numerous they will occupy the volume of our houses.

          Ah, but they've got a plan for that too — they'll just start making houses bigger!

          (what, you thought McMansions were just a silly affectation?!)

        • by ultranova (717540)

          Moore's law is ending in most of our lifetimes. When, exactly, is somewhat unclear, but the horizon is less than 40 years, at which point our single-atom transistors will be so numerous they will occupy the volume of our houses.

          You are assuming that we keep on building computers from transistors. But there are alternatives; for example, consider a mechanical adder made using benzene rings as gears. An adder made from molecular transistors would likely be far bigger.

          Also, you are thinking of transistor-anal

          • by Surt (22457)

            If we're not dealing with transistors, it's also the end of Moore's law, which is pretty explicitly about transistor density.
            http://en.wikipedia.org/wiki/Moore's_law [wikipedia.org]

            • by ultranova (717540)

              If we're not dealing with transistors, it's also the end of Moore's law, which is pretty explicitly about transistor density.

              Hard drives are usually considered to fall under Moore's law as well, despite the growth of their capacity having little to do with increasing transistor density. Also, the increasing density of maim memory is because - or at least requires - increasing density of capacitors. And finally, Moore's law is generally used in the context of increasing device capacity, not transistor densi

  • >> enabling more powerful smartphones, tablets, computers and gaming devices." So we can expect any battery powered device to last for 4 mins, compared to the 4 hours one can expect from a dual core mobile phone?
    • by Ibiwan (763664)
      Sorry, did you just say you only expect four hours from your phone? Out of curiosity, what brand do you have? (So I know to run the heck away from it)
  • Isn't this story a little vaporwarish? The companies "hope to develop" these new techniques and materials. There's no mention of an underlying discovery which the two companies might help each other commercialize. There's just this idea -- "Gee, wouldn't it be cool if we could do this? Let's look into it!" Is this actually news yet?

  • by currently_awake (1248758) on Wednesday September 07, 2011 @06:45PM (#37334474)
    Advantages: speed- Total execution time is based on distance the signal must travel- vertical stacking shortens distance. space- having half your motherboard used up for ram limits what you can do. If you ever want to see TB usb sticks you need this. Board space in a cellphone is very limited, with this you can multiply the number of chips on the board by 10/20/30 depending on how thin the slices are. cooling: you can etch channels on the backside before you glue to run cooling oil through.
    • Board space in a cellphone is very limited, with this you can multiply the number of chips on the board by 10/20/30 depending on how thin the slices are.

      But how many of these chips will be used for adding functionality, as opposed to adding measures to restrict the owner of a phone from making full use of the functionality? Case in point: the PlayStation 3 and PlayStation Vita have multicore CPUs and dedicate one core to DRM, and the Wii has an extra CPU (nicknamed "starlet") on the northbridge, again devoted to DRM.

      • by Splab (574204)

        Well from your fine examples we can conclude one chip will be used for DRM. How hard was that?

      • by josath (460165)
        Hmm, you've got a good point. We should definitely discourage any sort of technical advances, since those advances might be used for DRM!
    • by bgat (123664)

      A related benefit is that since they can assume that the signals never leave the chip stack, busses can be simpler and more fragile--- and faster.

      Even a stack of only two wafers is of huge benefit. Today's package-on-package chips (which are two wafers surrounded by two complete external packages including BGA pads) allow mobile phones to put the memory right on top of the CPU, which reduces chip count and space. Assembly at the die level instead takes that a substantial step forward, by getting rid of th

    • Your argument about TB USB sticks is right. Imagine SSD drives and portable media players that can actually hold a significant amount of your media collection.
  • These things will generate some heat, no doubt.

  • Use it to secure your Christmas presents!
  • Find some super-thermally conductive material, punch holes through the new bricks in several places (planning ahead of time to avoid stuff like, oh, circuits), place or thread the material into the holes and do a quick compress to ensure it fills up the hole and touches the entire length. Then connect the outside part of the conductor to whatever cheaper heat sink you want. Even if the inner conductor material is expensive at least it transfers the heat outside and away from the inner core.

    It would be even

    • Unfortunately, this would take too long and thus cost too much. Space is at a premium. You can't put a massive 1mm size hole in a wafer with 22nm features. We are talking about a 450mm (18-inch) diameter wafer that is about 900um thick. KOH etches Si at 1um/min. So it's take 450 minutes (7.5 hours) to etch through a wafer. Even if you limited each die to 1 hole, the wafer would be too fragile to survive the etch.
      • Being able to find out how is what research is for. Current chips shown to someone 40 years ago would cause this sort of reaction -> @_@

  • This article is a bit deceptive. IBM is not trying to create a package with 1000 high-end, high-power CPUs in it. Clearly, this would require 1000 times the thermal capacity in the cooling system, not to mention 40kW power supply to drive it and a pair of 40kA copper rails to bring all that current (at 1V) into and out of the package. This is not happening. The issue IBM is looking at is silicon defects. If you make a single MIPS processor per die, then you can get 10,000 of them on a wafer. If that wafer s
    • by slashfoxi (610738)
      Another thing I wanted to mention is that IBM makes it's money on flip-chip packages. Flip-chip is technically superior to wire-bond, but does not allow you to stack which is desirable for mobile devices (regulator on DRAM on CPU is a typical in a baseband package for your phone). What IBM really needs to come up with is a superior, proprietary stackable package so they can start making money on mobile.
  • Are they talking multiple die in the same package (Multi-Chip Packages) or multiple layers of Package-on-Package? Current MCP technology already allows 5 or so layers in a 1.4mm tall chip, while for Package-on-Package, it would be more difficult in keeping w/ any size constraints, but at least testing would be less expensive. But for servers, why don't they just have an optimal 4-core processor, and then have, say 32 of them in order to get that desired result? Something tells me this is being over-engin
  • by sgt scrub (869860)

    Glue?!? Everyone knows if you want it done right you use duct tape.

  • HAL in your pocket, doing double duty as a pocket-warmer heat-source for those long ice-skating parties. Awesome.

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