Help Build the World's First Community-Funded CPU ASIC

An anonymous reader writes "The 32-bit OpenRISC CPU has been available for many FPGAs and was turned into a commercial ASIC in 2003. Now, the OpenCores community is asking for donations to create a new ASIC with the OpenRISC CPU, ethernet, PCI, UART, USB and other peripherals. The goal is to be able to sell these ASICs at a low price to anyone who wants to build a cheap embedded system built completely on open source. The OpenRISC currently runs on Linux 2.6.37 and has ports of gcc 4.5.1 among other things."

Re:OK, I'll Say It

[Bryan3000000]

You don't understand. Chip fabricators will fabricate custom designed chips. Many companies have this done. Apple used to do it until they brought it in-house, and they still do for many components. If the design is actually completed and manufacturable, the only limit on price is the quantity of the order. This project can actually do what it intends.

Re:HDCaml

[olof_k]

Haven't heard of HDCaml before, but the idea of inventing a nicer languange than Verilog and VHDL lives on. System Verilog adds a lot of syntactic sugar and new functionality, and there is a cool project called MyHDL that uses Python. System Verilog is gaining popularity in the industry, but unfortunately there aren't any open source tools to work with it yet. The commercial ones don't seem to implement the full language either. A bit like the HTML5 situation. We could really need something though. Even after having spent nearly ten yers doing hardware design, I find the two main languages horrible to work with.

Re:My dream is a free SPARC T2!

[the linux geek]

You don't want a SPARC T2, T3, or any other recent SPARC design in your desktop or laptop. Performance of a T3 is, accoridng to SPEC, very similar to a hugely cheaper and less power-hungry AMD Magny-Cours for massive-threaded applications... and much, much worse for few-thread apps. The "high-end" Fujitsu SPARC64 VII+ is also pretty damn slow.

Prices

[Anonymous Coward]

I work for a company that produces outsourcing for ASIC supply chain. Assuming a 130nm process, we are talking about $750K for masks and the like and $250k for Non-recurring engineering. Manufacturing run requirements would be a half lot at 8 inch- 12 wafers at probably 100-150 units per wafer MINIMUM.So expect a production run of at least a thousand.

I don't think this project can be done on commercial terms.

Re:OK, I'll Say It

[Anonymous Coward]

No, you don't understand.

From the GP:

No one has chip fabs in their basement. So someone will have to pay big money to make the masks and tape-out and test the hardware. Unless some major vendor picks up the design and mass produces it lots of 100s of thousands, the price per CPU is going to be stupidly more expensive than an off-the-shelf CPU/motherboard or embedded system. And, even then, you are probably buying an overpriced, underpowered CPU just because it is "free."

Repeat this until reality sinks in. He's not saying that chip fabricators won't fabricate custom chips. He's saying that the cost of getting them to do so is prohibitive. If your order volume is small, the fixed costs will eat you alive.

As for the project doing what it intends... the mission statement on the beg-for-donations page linked up above is full of monumentally dumb claims about how this is could revolutionize the industry and make the multinational giants quake in their boots. Yeah, right. The "multinational giants" and even the smaller players are busy working on chips which have reasonable technical specs for 2011 and beyond. These guys are making a trailing-edge toy which will have little appeal outside the niche of "people who must have everything in their computing lives approved by RMS".

Allow me to support that assertion. I've looked at the "detailed" technical plan, which is anything but detailed. There is a block level view of what's going in, which is mostly off-the-shelf OpenCores cores, but there are no detailed plans about how this is going to be translated into an actual ASIC design. There are only plans for making a FPGA based development platform.

Don't get me wrong, a FPGA platform is a good thing to do. A project like this won't have the resources to do very much design validation through simulation (which requires lots of people writing tests and running sims, i.e. real money), so FPGA based prototyping and validation is even more important than it is for conventional "closed source" ASIC projects. However, there is no plan given for how they're going to take their working FPGA design and turn it into an ASIC design. There isn't even any mention of which fab vendors and processes they're thinking of targeting. (and yes, these things matter immensely when you're making a chip.)

It's somewhat revealing that they're using a single small Altera Cyclone IV FPGA (under $60 qty 1 through Digikey). If you don't understand the significance, this means their design is tiny and trivial and low tech by current standards. The big boys they're planning to make quake in their boots need multiple ~$5K to $10K ea. FPGAs (big ones with well over 10x the resources of the FPGA the opencores guys are using) to fit all the logic in their upcoming System-on-Chip ASIC designs.

I suspect that if fully laid out their plan is something like "Build the FPGA version, and surely the ASIC guys will come knocking on our door with money to translate our awesome design into a chip!" But this will never happen, because their FPGA design is years behind the state of the art. They're competing against hordes of low cost chips which already do the same things and have already paid back their cost of development.