Intel, Toshiba, Samsung To Form Chip Alliance

Lucas123 writes "According to a report from a Japanese news agency, semi-conductor leaders Intel, Samsung and Toshiba are forming a development alliance to halve the size of chip circuitry in order to create more dense NAND flash chips and more powerful processors. The vendors would not confirm the news report, but the Nikkei Daily said they hope to reduce lithography technology from the 20 nanometer size used today to something below 10nm. The news agency also said Japan's Ministry of Economy, Trade and Industry may fund up to half the project's cost, or roughly $61 million."

And a side-deal?

[sosaited]

An alliance of this sort most probably also means some price fixing deals already on the table. But if we get some decent capacity SSD's for reasonable price a bit sooner, for a few bucks more, I think its worth it.

Intel at it again...

[RocketRabbit]

Intel is starting to feel the heat from ARM. Sooner than later datacenters will be running on ARM processors, and doing the same work per time unit at a fraction of the power cost.

This is a new market that they wish to stomp on before it can get started.

Re:Intel at it again...

[Required Snark]

There is a certain amount of irony in all of this. When RISC was invented it was suppose to displace CISC because of better performance due to a more efficient architecture that used fewer gates. INTEL, AMD and other i86 vendors were able to fight back by using RISC internally in their micro-architectures. This succeeded because of the standardization and network effect based around the generic i86 platform. For example, the MIPS CPU and Sun's SPARC never succeeded on the desk top once the price performance of the i86 got good enough.

So now INTEL and the i86 are facing intrusion from the bottom, because the ARM cpu is a RISC design that provides better performance due to a more efficient architecture with fewer gates AT LOW POWER CONSUMPTION. Finally there is a situation where the superior characteristics of RISC will win because a CISC cpu cannot compete. Power usage is the Achilles heal of the CISC design.

The only thing that the ARM lacks to become dominant in the sever room, and even in supercomputing is a 64 bit variant. With multi-cores and 64 bits power usage will be the deciding factor. Any guesses when this will happen?

Re:Intel at it again...

[Required Snark]

Oooh, I must have hit a nerve. First, read what I said:

the ARM cpu is a RISC design that provides better performance due to a more efficient architecture with fewer gates AT LOW POWER CONSUMPTION.

The key word here is efficient. Specifically I am talking about operations per watt. If some combination of heat dissipation and cost to run the system are limiting factors, then this kind of efficiency is important.

I am not the only one who thinks this way. IBM has also made a system that chose lower power CPUs to build a supercomputer: the Blue Gene/L. http://en.wikipedia.org/wiki/Blue_Gene#Major_features [wikipedia.org] To quote the article "Trading the speed of processors for lower power consumption." This machine had two Power PC cores per node, which each being a 700 MHz PPC 440, not exactly a screaming demon of a CPU. The upgrade, the Blue Gene/P has four 850 MHz PPC processors per node. Still not blindingly fast. The next version, the Q model, out sometime soon, will continue to use even more relative low speed processors, "1.6 million processor cores" according to the article.

I can't immediately find the details online, but I think that the reason that there were so many AMD based supercomputers at one point was that the AMD CPUs, even though they were slower then the competing INTEL units, were more efficient in flops per watt.

So I will restate what I said in the original post in more detail. I think that people will start using ARM processors in server rooms in the near term. This is a no brainer. Also, someone will extend the ARM to handle 64 bit data paths, including 64 bit floating point. When that happens, ARM chips will be used to make supercomputers. Because they are IP can can be customized at the silicon level, in supercomputing multiple CPUs will be on a chip that includes some of the inter-processor communications hardware. It will be very hard for the i86 architecture to compete because it is a CISC, not a RISC.

I hope this clears it up for you.