Intel, Toshiba, Samsung To Form Chip Alliance

Lucas123 writes "According to a report from a Japanese news agency, semi-conductor leaders Intel, Samsung and Toshiba are forming a development alliance to halve the size of chip circuitry in order to create more dense NAND flash chips and more powerful processors. The vendors would not confirm the news report, but the Nikkei Daily said they hope to reduce lithography technology from the 20 nanometer size used today to something below 10nm. The news agency also said Japan's Ministry of Economy, Trade and Industry may fund up to half the project's cost, or roughly $61 million."

Alliance?

[nurb432]

Or collusion?

Halve, or quarter the size?

[noidentity]

they hope to reduce lithography technology from the 20 nanometer size used today to something below 10nm

Wouldn't this allow quartering the size, since you have this halving in both dimensions?

Re:Halve, or quarter the size?

[Twinbee]

Whenever it comes to this kind of thing, it's always left ambiguous. I find that generally when people (even professionals) speak of 'half the size', they could mean in length, area, or volume (where applicable). Each of those of course gives entirely different results.

I think personally the best idea is to use the highest dimension for the application. For example, when speaking of a 3D object, half the size would mean half the volume. Unfortunately, things like DPI don't work like that.

Re:Intel at it again...

[Wrath0fb0b]

So now INTEL and the i86 are facing intrusion from the bottom, because the ARM cpu is a RISC design that provides better performance due to a more efficient architecture with fewer gates AT LOW POWER CONSUMPTION.

What are you talking about? ARM provides lower performance at lower power consumption.

I work on high performance clusters (usually SGE/ROCKS not Beowulf, sorry guys) dedicated to physical and biological simulations and there is just no chance the ARM is taking over. We are pushing the bounds of our chips (all Nehalem-based Xeons) already, going to back to PIII-era performance would be a huge setback. There's just not a lot of competition with superscalar out-of-order x86-64, although specialized machines are really cool.

Oh, and for those that say just use more of the lower-power chips, efficient parallelization is really ****ing hard, even in the simulation world. We routinely push the latency bounds of our interconnects (infiniband, usually) when farming out even large jobs. Telling my boss that we can achieve some power savings at the cost of buying 4x more expensive networking gear is going to lead to either a hearty laugh or a pink slip (or both!).