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Marvell Launches First Triple-Core Hybrid ARM Chip 117

Posted by kdawson
from the just-a-trickle dept.
Blacklaw passes along an excerpt from Thing.co.uk that begins "While other manufacturers are content to develop dual-core ARM processors, Marvell has gone one better — literally — with a new triple-core chip called the Armada 628. The system-on-chip design, based on ARM's v7 MP series, features two dedicated 1.5GHz processing cores plus a third 624MHz core in a single application processor — making Marvell the first company to bring such a beast to market. While two of the cores are a pretty standard SMP setup, as seen in other dual-core ARM implementations, the third is a standalone processor designed for ultra-low-power draw. The idea behind such a design is that when the system is idle, or only running a low-performance application on a single thread, it can shut off the dual-core portion and save oodles of power."
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Marvell Launches First Triple-Core Hybrid ARM Chip

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  • Iron Man (Score:1, Offtopic)

    by geekoid (135745)

    Now with the power of ARM!

    • Re: (Score:3, Funny)

      Does it run on DC?

      • Re: (Score:3, Funny)

        by ajlitt (19055)
        No, Marvell.
        • Re:Iron Man (Score:4, Informative)

          by kimvette (919543) on Thursday September 23, 2010 @04:04PM (#33680338) Homepage Journal

          Oh come on, that was FUNNY, not OFFTOPIC.

          Attention uninformed moderator: DC and Marvel are both comic book publishers. In fact have for decades been rival companies and each "universe" is known for certain superheroes. On the DC side you have Superman, Batman, Wonder Woman, Teen Titans, and so on. The Marvel universe features The Amazing Spider Man, X Men, Fantastic Four, Daredevil, Iron Man, and so on. Heck, with all the comic book-based movies over the last 20 years, even women know about comic books, and not just the geeky ones among us.

          In other words, parent post was a topical JOKE (NOT OFFTOPIC), and you should instead focus on modding "insightful" and "informative" posts UP rather than modding posts you disagree with or jokes you don't get "down". In other words, follow the moderation guidelines - and consider developing your sense of humor while you're at it.

          HTH!

        • by RebootKid (712142)
          mod parent funny
  • Wait... (Score:4, Interesting)

    by CajunArson (465943) on Thursday September 23, 2010 @12:10PM (#33677370) Journal

    Why can't it just shut down one of the two normal cores, and run the other core at a highly reduced rate to get the same power savings? Additionally, I've seen plenty of benchmarks where a higher-power draw chip that can get done with a task quickly and drop back to low-power idle mode is actually more energy efficient than a lower-power chip that takes longer to get the task done. What sort of tasks is the third core intended to do that it would be so much more efficient than a regular ARM core?

    • IDK. Maybe because it uses a modified architecture that is more efficient, but because of that nature it can't scale up as high? Maybe max speed itself also determines efficiency passively.
      • I actually decided to read tfa to clarify.

        the third is a standalone processor designed for ultra-low-power draw

        Sounds like it was an architecture thing. IANA compute chipologist though.

    • Re:Wait... (Score:4, Informative)

      by santax (1541065) on Thursday September 23, 2010 @12:18PM (#33677492)
      From the full article: While two of the cores are a pretty standard SMP setup, as seen in other dual-core ARM implementations, the third is a standalone processor designed for ultra-low-power draw. The idea behind such a design is that when the system is idle, or only running a low-performance application on a single thread, it can shut off the dual-core portion and save oodles of power. So, they have designed that third core from the ground up with powerconsumption in mind. Whereas the 'normal' cpu's are designed with speed, processing-power and scalability in mind.
      • Re: (Score:3, Insightful)

        by CajunArson (465943)

        That doesn't really answer my question though. First what does "standalone" mean? Any CPU that can access memory and run a process could be called "standalone". Second.. you mentioned power draw which is nice, but also not the important factor. The important factor is ENERGY efficiency. As an example: A 100 watt power draw from a CPU that takes 1 second to finish a task is more energy efficient than a 10 watt power drawn that takes 12 seconds to finish the same task. In the case of the faster ARM core

        • by Zerth (26112)

          The point of the third processor is not efficiency, it is low power. As you said, chips that are designed to be low power aren't necessarily efficient. Similarly, lots of chips have a idle/watchdog mode, but they aren't as low power as a chip designed to do that.

          This way you can have the third core do event detection and last a long time on very little power, but then wake up the dual-core to process the events quickly and efficiently before going back to sleep.

        • by sunking2 (521698)
          Imagine an application that only logs key strokes. Which would you rather run on from a power stand point? Extreme and silly example, but point is this is probably geared toward things that are interaction bound with plenty of idle time. And their belief seems to be that it saves them power to run on a slower more power efficient core.
        • Re:Wait... (Score:4, Insightful)

          by xouumalperxe (815707) on Thursday September 23, 2010 @01:07PM (#33678186)

          The important factor is ENERGY efficiency. As an example: A 100 watt power draw from a CPU that takes 1 second to finish a task is more energy efficient than a 10 watt power drawn that takes 12 seconds to finish the same task

          What if the task at hand is a continuous, undemanding one, like, say, basic mobile phone functions?

        • by medv4380 (1604309)
          It's like designing a car engine. You can build it for high horse power or you can build it for low horsepower to improve the mileage. It is very hard to get the highest horse power and th best gas mileage using the same design and even if possible you'd have to redo the timing when you wanted to change from one to the other and that's not something you do while it's running. They decided that they can put two different engines in this chip. One designed for performance with a duel core and one designed
          • by espiesp (1251084)

            While I don't disagree with your point either in principle or in practice, there is something one of us is confused on.

            You mention "timing", I'm assuming it's in reference to the engine. Ignition timing changes with engine speed and load in virtually every EFI vehicle made in the past 30 years. Also, cam timing, on both intake and exhaust valves, is variable (whether in steps or 'infinitely') on-the-fly in a huge number of vehicles built today and for the past 20 years has been done in mass produced vehicle

            • by medv4380 (1604309)
              I'll admit I'm probably more then a little confused on timing. My primary experience with timing is my old friends from HS 15 years ago who always wanted to mess with their cars timing belts to improve the horse power on their old 57 Chevy classics.
        • by MightyYar (622222)

          As an example: A 100 watt power draw from a CPU that takes 1 second to finish a task is more energy efficient than a 10 watt power drawn that takes 12 seconds to finish the same task.

          This is only true if the "task" has a finite duration. If the task is continuous, then the lower-power chip wins, provided it is powerful enough. For example, if the "task" is "sit there and wait for the phone to ring", then whichever chip can consume the least power while doing almost nothing wins.

        • by PCM2 (4486) on Thursday September 23, 2010 @02:14PM (#33678878) Homepage

          I think we're tripping up over the reporter's choice of language here. From Marvell's actual press release [prnewswire.com]:

          The tri-core design integrates two high performance symmetric multiprocessing cores and a third core optimized for ultra low-power. The third core is designed to support routine user tasks and acts as a system management processor to monitor and dynamically scale power and performance.

          Depending on what their definition of "routine user tasks" might be, it sounds like it doesn't actually shut off both cores and run exclusively off the third core, the way TFA makes it sound -- it only does that if the device isn't doing anything. More interesting stuff:

          Marvell's ARMADA 628 tri-core CPU comprises a complete SoC design – a first for the industry. In addition to the tri-core CPU, there are six additional processing engines to support stunning 3D graphics, 1080p video encode/decode, ultra high fidelity audio, advanced cryptography, and digital photo data processing – for a total of nine dedicated core functions.

          This sounds like a pretty cool chip.

      • Re: (Score:3, Interesting)

        by david.given (6740)

        Looks to me like this is designed for the mobile market: two SMP processors to run the application OS, one lower-power processor to run the radio OS. Pretty much every smartphone on the market works like this, albeit with a single application processor.

        The reason is that GSM (and most likely CDMA, although I've no experience of that) is critically real-time and needs a real-time OS to manage: Linux basically doesn't cut it. So you dedicate a complete processor with its own real-time operating system to it

    • Re: (Score:1, Offtopic)

      by jd (1658)

      Because superheros never work well on reduced power? Or maybe there's a patch they'll sell later (as per Intel's "upgradeable processor") that will let you run all three.

    • Re: (Score:3, Interesting)

      by pclminion (145572)
      *shrug* -- Even in seemingly low-requirements applications like a laser printer you'll typically find at least two or three microprocessors. It's common for those CPUs to be running at different clock speeds, be closer or farther away from certain kinds of memory, and dedicated to specific tasks. You might have the main core running Linux with a firmware RIP engine while some subsidiary core runs a custom RTOS to drive the print mechanism. This new CPU is just packaging a few of those heterogeneous cores up
    • leakage (Score:5, Interesting)

      by YesIAmAScript (886271) on Thursday September 23, 2010 @12:39PM (#33677788)

      At current processes (44nm, 32nm, etc.), switching power isn't critical at low speeds, it's leakage that is the issue. So a fast (big) processor takes a fair amount of power even if you run it slow.

      Whereas a slow core is smaller, so that means fewer transistors to leak. You also can make the gates out of lower-leakage cells, so that even when on they leak less. This limits top speed which would be a problem for the main core but isn't a problem for this non-main core.

      Having additional low-power cores isn't that strange, many current phone SOCs do this. What is unusual is most of those have one main core and many slower ones and this one has two main cores and one slower one.

    • Will it ever run all 3 cores at once?
      • by owlstead (636356)

        Good question, I haven't found out yet. But I presume that is all in the software, which might make it a tricky processor to program for. I cannot see it transfer all state from one core to one of the faster ones without some help of software in the operating system. And if it does run all three processors at the same time, you will basically have an ASMP. So it is an interesting design, even though it is rather obvious. It is not hard to see ASMP's become more common ground on SoC's (you just don't need ea

    • Cores can be optimized for low power consumption or high performance. A core that can switch between a performance mode and a low power mode is probably making compromises on both modes. If you have completely different cores your can avoid such compromises and maximize performance in one core and minimize power consumption in the other. Having heterogeneous cores most likely yields better results than any mode switching scheme.
    • I've seen plenty of benchmarks where a higher-power draw chip that can get done with a task quickly and drop back to low-power idle mode is actually more energy efficient than a lower-power chip that takes longer to get the task done.

      Maybe if you have to do some simple task very frequently? Seems like a realistic usage scenario for this kind of chip.

    • by j1m+5n0w (749199)

      Why can't it just shut down one of the two normal cores, and run the other core at a highly reduced rate to get the same power savings?

      I'm not really the expert at hardware design, but I'd guess that the energy savings from reducing the clock on a high-speed chip aren't all that dramatic. If you have a 1.5 ghz chip, it has to be designed around circuits that can reach a stable state in less than a nanosecond. A chip clocked at a third the speed can use longer wires and more complex circuits, and probably

      • by bytta (904762)
        I don't have a car analogy for this, but can't this be compared to a gas stove that must always have a fire going?
        The new chip is like a dual-burner model with the third one acting as a pilot light, which makes a lot more sense than running one of the burners at its lowest setting...
    • Check the data-sheets? I've been writing code on ARM for 6 years now and I can't recall any devices having a dynamic or software-set clock rate... I'm just blindly assuming there is a reason for that. I also think technologies like Intel SpeedStep shut down paths as well as dropping clock rates, and I also have no idea just how much SpeedStep actually saves. If anyone has any numbers I'd love to see them, but I'm too lazy to try and remember login credentials to download datasheets and figure out W@[Hz] .
      • by dmitrygr (736758)
        Seriously? What ARMS have you worked with? Every one I've seen has ability to set speed

        Intel PXA gen1 series have software settable MEMORY and CPU speeds with 12MHz granularity
        Intel PXA gen2 series have software settable BUS, MEMORY, AND CPU speeds with 13MHz granularity
        Freescale i.MX series have software settable MEMORY and CPU speeds, with sub-Hz granularity
        TI's older OMAPs can set CPU speed with 6 MHz granularity
        • Mainly game systems and media devices but a few mechatronic devices as well. To be honest I've never actually tried to set the speed so I basically just didn't know you could. The only time I've laid out a board with an ARM core I used a Renesas package and a clock crystal and that board had no need to save power so I didn't even think about it.
    • Running a fast core at low speed saves a good amount of power, but running a core designed for that low speed is even lower power. The transistors in the third core are physically different, mostly to reduce the leakage power, which is wasted power from transistors that can't be turned off all the way. Designers have to make a tradeoff between speed and power in their transistors. A fast transistor lets electrons through quickly when the transistor turns on, but is bad at keeping electrons from passing thro

  • Maverllous!
    • by Smauler (915644)

      Erm... what? You've just managed to misspell marvellous, despite the company being called Marvell... all you had to do was add "ous" to the end. Marvel is the root of marvellous.

      If I'm missing something here... well, it won't be the first time.

      • by PmanAce (1679902)
        Nah you are not missing anything, I just wrote something early in the morning without having had my coffee. You just knit-picked the hell out of my comment.
  • Intel should be seriously worried about their creep into netbooks. Intel brought the notebook market to all time low prices with atom and things like this chip might turn around and bite them in the ass.
    • Same was said in the 1990's when Acorn Computers had machines that were faster than Intel's own Pentium and 486 machines. RISCOS was pretty much better than Windows 3.1 at the time too. *weeps*

    • Re: (Score:1, Interesting)

      by Anonymous Coward

      You have it backwards. The Atom parts are a partial response to ARM and not a cause for it. ARM already ships a large multiple more CPUs than x86 and is starting to eat into the traditional x86 market via smart phones, tablets, set top boxes/appliances, and servers. Intel has responded by producing 'low power' Atoms and running around trying to convince phone manufacturers that 2 hours of battery life would be worth it for 'the full internet experience(flash and legacy windows crap)'. However it's also

    • Intel should be seriously worried about their creep into netbooks.

      Ahh...you....

      Bwahahahahahahahahahahahahahaha! Heh...heh... And ..and..any day now there will be smartbooks everywhere!

      --bornagainpenguin

      PS:Wake me up when they FINALLY release these things in a smartbook device about the size of the HP Jordana hand held PCs...then maybe I'll be interested, otherwise this is just more vaporware.

  • by DevConcepts (1194347) on Thursday September 23, 2010 @12:15PM (#33677422)

    Beowulf Cluster of...... Never Mind......

  • by imag0 (605684) on Thursday September 23, 2010 @12:21PM (#33677534) Homepage

    Reminds me of This old chestnut [theonion.com] from the Onion.

    Stop. I just had a stroke of genius. Are you ready? Open your mouth, baby birds, cause Mama's about to drop you one sweet, fat nightcrawler. Here she comes: Put another core on that fucker, too. That's right. Three cores, one chip, and make the third one play MP3's or someshit. You heard me--the third core plays MP3's. It's a whole new way to think about computing. Don't question it. Don't say a word. Just key the music, and call the chorus girls, because we're on the edge--the razor's edge--and I feel like dancing.

    • Re: (Score:2, Interesting)

      by Walterk (124748)

      Sometimes reality is stranger than fiction: http://www.amazon.co.uk/Gillette-Fusion-Manual-Razor-Replacement/dp/B000GE5712 [amazon.co.uk]

      • Every time I see those advertised I think back to that Onion article.

        Stopped buying Gillette blades around that time too. It seemed to me that their 2-blad razors suddenly got a lot blunter, so I switched over to Wilkinson Sword's twin-blade system. Which is much sharper and thus more comfortable.

        • by elsJake (1129889)
          I've switched to Wilkinson double sword , classic double edge blades , sharper than anything else and a lot cheaper too.
          The fact that they're cheaper also helps with comfort because you feel more inclined to change them before they ware out.
          Haven't had a problem yet but i am considering switching to a straight razor as soon as i can buy myself a Dovo. Sure enough you need to be careful but the increase in comfort and quality of the shave are at least the same as the switch from crap razors to Wilkinson. Mor
        • If you like that, you'll really like double edge razors. You can get a decent handle on Amazon for $9 and the blades get to as low as $.17 a piece for decent blades. Yeah you'll spend a little more to get a decent brush, sample pack of a variety of razor blade brands, and soap and stuff, but you'll never regret it. Anyone that is sick of paying absurd prices for cartridge razors should consider it as well. It does take a little more time, but it's well worth the better shave and knowledge that you're not su
    • Re: (Score:1, Funny)

      by Anonymous Coward

      there is also an old saturday night live sketch from either the second or third episode of the first season that is pretty much the same joke. except the sketch was making fun of manufacturers of two blade razors and one upping them with then-fictitious three blade razors

  • I guess they're trying to get a LEG up on the competition.
  • by Animats (122034) on Thursday September 23, 2010 @12:30PM (#33677664) Homepage

    There's a tendency to put a little CPU in devices to handle activity when the device is "off". Something has to sit there and watch for the remote if the TV is to be turned on remotely. Many machines have a "wake on LAN" capability, and most servers have an extensive remote management capability built into the network controller. All of these imply some little CPU, invisible to the main operating system, doing things when the device is supposedly "off".

    This isn't necessarily a bad thing, but it does provide an attack surface. Especially since those little machines tend to have very powerful access to the rest of the system, bypassing most security measures.

    This new chip looks like an effort to integrate the "power off" CPU onto the same silicon as the main CPUs. That's a routine use of silicon real estate by putting more on one part. But the concept isn't new.

    • by xonicx (1009245)
      Embedded System on Chip= ARM cores + Peripheral(SDIO, USB, I2C..) Controllers + Video/Audio Decoder + Interrupt Controller + Power Manager Unit Controller + RTC + ... Most of the SoCs are designed to have different power rails to all ( or few combinations) of these modules. I am not aware of any SoC which keeps ARM core running while playing music when screen is OFF. To serve an interrupt, you don't need to keep ARM running. You can always wakeup ARM core through some custom circuitry and save power.
      • by fatphil (181876)
        Regarding your 'I am not aware ...', here's a powertop summary of an mp3 playing on high end ARM-powered mobile phone with no other apps active:

        Freq: 500MHz 3.4%, 250MHz 96.6%
        IRQs in 30s: DMA 3200, [elided] 2150, programable timer 1880, i2c 640
        Core power domain: Off 0%, Retention 0%, Inactive 48%, On 51%
        (other powrdomains like graphics-related stuff: 100% off)
        Total wake-ups 10000 = 333/s, Total IRQs 8000 = 266/s, Timers 2000 = 66/s
        H/W wakeups 100 = 3.3/s

        (OK that was on prototype hardware, but not significan
    • by owlstead (636356)

      They market it as a 3 core CPU. This more or less implies that the slower core is still fully ARMed. This also implies that it will be a nice challenge for operating system engineers: what are you going to run on the slower core and what will you run on the faster one? Can you move one thread from the one core to the other ones, and how easy is this? How do you handle applications that don't play nice and keep using large quantities of CPU time after you've told them to go into sleep mode? This is rather di

      • by amorsen (7485)

        How do you handle applications that don't play nice and keep using large quantities of CPU time after you've told them to go into sleep mode?

        You're the bloody OS! You don't have to give the applications any CPU time at all, if you feel it's time better spent playing tic-tac-toe with imaginary opponents.

        It's tricky to switch from the fast to the slow CPU and back at precisely the right point, but all you lose by getting the timing wrong is slightly worse performance or slightly worse battery life. Not the end of the world.

        • by owlstead (636356)

          Sure thing, but you still have to program the OS to do it, and for now each and every CPU has evenly matched cores. If you look at the mainstream desktop operating systems, they are all assuming that every core is equal to all the other cores. Then you've got the Cell computer which is a single CPU and multiple "Cell" CPU's. This is a different beast altogether - each and every program can be switched from one core to the other, but there is one special CPU that is much slower. So your scheduler has to be a

          • by amorsen (7485)

            This is something which has been researched in computer science for a long time. See e.g. Amoeba distributed OS (which assumes completely different architectures and disjoint memory).

            You could do a good first attempt with Linux and a userspace manager process which changes CPU-affinity based on program requirements and load. This only works because the differences are so simple in this case, but I bet hardware designers will try to keep it reasonably simple.

            • by owlstead (636356)

              Oh, I know about the Amoeba OS, that project got started at the VU in Amsterdam while I was studying there (not that I would recommend the place for its educational capabilities, but that's another discussion).

              I wonder though if these kind of projects are of any use to current operating systems. Amoebe is a research project by Tanenbaum, and he's well known to not care too much about actual use within the field. A (very) quick look at Amoebe shows me a system that is rather different than current operating

              • by owlstead (636356)

                And anyway, it seems that Amoebe uses process distribution rather than thread distribution. I don't know if these "processes" map directly to the processes found on common OS's, but this seems the case. That fact alone makes Amoebe scheduling absolutely worthless in my opinion.

                It (Amoeba) has also been created to reflect very fast processors in a distributed environment with slow interconnects. This is not at all the case with multi-core chips. I think that Amoeba and this ARM chip are so far apart that it

  • by bhcompy (1877290)
    You have the right to bear ARMS, don't let any authoritarian inner-city councilman tell you otherwise
    • Re: (Score:3, Funny)

      by durrr (1316311)
      Well, there are agreements which prohibits the use of Multiple Independent RISC Vehicles in your devices.
      Though i guess you're fine as long as the russians don't find out.
    • by mjwx (966435)

      You have the right to bear ARMS, don't let any authoritarian inner-city councilman tell you otherwise

      I would never dare to infringe upon your right to have furry sleeves.

  • Fuck everything, we're doing 7 cores!

    • by fatphil (181876)
      You're behind the curve, the cell had 9 cores.

      Although in reality most smartphones will have about 5 ARM cores in them. There really aren't that many ASICs as there used to be, many are just general purpose processors, perhaps with that tell-tale sign - 'firmware'. Your wireless card - I bet you there's an ARM core in it. Your bluetooth chip too? Ditto.
  • Will we rate multiple oodles in binary or standard method? Kilooodles or Kibioodles? Megaoodles or Mebioodles? Gigaoodles or Gibioodles?

    INQUIRING MINDS WANT TO KNOW!

  • Power != Energy (Score:5, Interesting)

    by Theovon (109752) on Thursday September 23, 2010 @01:22PM (#33678338)

    It's common for people (myself included) to conflate Energy with Power, but it's often an important distinction. To begin with, technically, we don't consume power. We consume energy (to do work, which is in the same units), and power is the rate at which it is consumed.

    An important factor often left on the floor is processing efficiency, meaning how fast are we getting work done for a given power level. If you reduce power by half, but the work takes twice as long, you've accomplished nothing. For the same amount of work, your battery will drain the same amount. Indeed, what we really want to do here is make systems take less energy, and within reasonable limits, it doesn't matter how much power you consume while you're doing it.

    This has actually been one of the things that makes ARM processors energy-efficient. Not to say they're not also low power, the strategy has always been to build event-driven systems. Something happens (user input, sensor reading, etc.), which causes the CPU to wake up in your embedded system. The ARM processor then blasts through the work to be done, and then goes to sleep, powering down completely until the next event. (Some systems will use intermediate "sleep" states that are less time-expensive to sleep and wake.) An ARM is more efficient than an Atom, in part because it uses less power, but also in part becauses it needs less time to complete the same task.

    In today's technology, this is especially important. At 90nm and 65nm, the Intel Core and Core 2 used clock gating to save power. Functional units (e.g. floating point multiply) that are idle have their clock signals gated, which reduces power being used by that part of the clock distribution tree. This is important because in those technologies, dynamic (switching) power dominates. In the Core i7, Intel uses POWER gating. When a functional unit is idle, it's powered down completely. This is because in 45nm and 32nm CMOS, static (leakage) power is what dominates.

    Going back to ARM, this is something being applied in the Cortex A9. They've made a more complex processor in order to execute out of order, but as a result, computation goes appreciably faster. During computation, leakage is constant. By getting the work done faster and powering down completely, more leakage power is saved. Less time translates into less energy, even if the A9 uses more power than the A8.

    • Re: (Score:3, Informative)

      Processing efficiency is ARM's whole focus. They usually talk about the performance per milliwatt of their chips. This is why they never compare themselves to Intel or AMD, which focus on performance, and why most hand-helds use ARM based processors (PSP, Nintendo DS, iPhone, basically every single Android device, etc). If your device runs on a battery this makes good sense unless you have to have x86 compatibility.
  • They're not the first, there's nothing different about this, and it's not even to market.

    "Triple core" as they describe it is pretty standard stuff in the embedded/mobile world. You have one or two main "application" cores, and one or more I/O processing cores doing DSP, graphics, data processing, low rate data moves, etc. Just have a look at an NVidia Tegra 2, or even a Tegra 1 marketing slide and you'll see it has even more cores than this Marvell chip. Better yet, any Qualcomm 1GHz class cell phone chip

    • by amorsen (7485)

      The difference is that this one seems to be able to run all three cores as SMP with a single kernel being able to run on all of them. Traditionally the cores either run completely different systems, or the kernel runs on one along with general system tasks, whereas the other is dedicated to DSP-like work.

      • by pslam (97660)

        The difference is that this one seems to be able to run all three cores as SMP with a single kernel being able to run on all of them. Traditionally the cores either run completely different systems, or the kernel runs on one along with general system tasks, whereas the other is dedicated to DSP-like work.

        Except they're not Symmetric. If you go to Marvell's main site and look at the larger press release, it calls them - and note the use of "quote marks" here: "Heterogeneous multiprocessing". As in, not sym

        • by fatphil (181876)
          "Why would you want a third core which runs at a fraction the speed of the other two"

          Presumably as it's a simpler core with fewer optional modules (jazelle, (vector) floating point, thumb modes, ...), with a much lower transister count, smaller cache, less leakage, and lover voltage OPPs, so that at 600MHz it comsumes less than 600/1500 of what the big cortex cores use.

          But that's a WSITD.
        • by amorsen (7485)

          Is their mips-per-milliwatt rating so bad they actually need the 3rd core for decent idling?

          The mips-per-milliwatt is not the problem. The problem is the leakage current when in a sleep state higher than completely off.

          • by pslam (97660)

            The mips-per-milliwatt is not the problem. The problem is the leakage current when in a sleep state higher than completely off.

            I will change my question to: Is their SoC system design so bad that they can't power down all of the application cores? That's the whole point of having all those extra I/O and DSP cores: you don't need the "application" cores up and running when you're almost-idling playing an MP3 or something.

            To be fair, it's an interesting idea having an extra core with lower leakage and more

    • by PCM2 (4486)

      "Triple core" as they describe it is pretty standard stuff in the embedded/mobile world. You have one or two main "application" cores, and one or more I/O processing cores doing DSP, graphics, data processing, low rate data moves, etc.

      "One or two" isn't the same as three. This chip has three application cores and six I/O or DSP cores like you describe.

      • by pslam (97660)

        "One or two" isn't the same as three. This chip has three application cores and six I/O or DSP cores like you describe.

        It has two symmetric cores and a third of a different design which just happens to be compliant to the same spec (ARM-v7) and cache coherent. That doesn't make it "Tri-core". It's arbitrary how many they pick to claim it is. Hell, NVidia was claiming Tegra 2 was the world's first 7 core processor a while back, because they simply counted number of cores. You could probably run the OS on m

        • by owlstead (636356)

          Personally, I read it as a three core chip, where one of the chips is the controller (since the others could be powered down). I'm not certain of it though, since there is just not enough information about it on the internet.

          Furthermore, I think it says in their press release that they are sampling to OEM's. That does not sound like vaporware, even though it is not produced in quantity just yet. It does normally mean that for most part their processor design is done.

          But I'll probably completely wrong about

        • by PCM2 (4486)

          Well look, maybe it's not as revolutionary as the press release makes it sound. It's probably best seen as an incremental innovation in a very crowded market. But if you look at it another way, the ARM market is so crowded that it really wouldn't make any sense to put out a new chip that wasn't actually innovative in some way. If it's not cheaper, it has to be better, or else OEMs will pick someone else's chip -- it's not like there's any shortage of them.

    • by xSacha (1000771)

      Did you ever think: Perhaps there's a reason they are saying this? No one else has ever claimed this.
      They also claim that you can run music just using the third processor and get 140 hours of playback (standard battery) or 10 hours of video playback.
      Considering there's 6 other DSP/IO cores on there, why would they have to use the third core for anything but idling?

      It seems the third core has better scaling on it afforded by not having higher scaling on it. Perhaps enabling lower voltage/clock levels than th

  • Why do I keep seeing articles about new super-powerful ARM7 chips, when ARM9 has been out for a long while? Even my Nintendo DS has an ARM9, so I can't imagine it is that ARM9 is too big or complicated or inefficient.

    • Re: (Score:3, Informative)

      by Halo1 (136547)

      ARM is very good at confusing numbering schemes. There are basically two separate numbers: the architecture version and the cpu model number. The ARMv7 (note the *v*) in the article is about the architecture version (ARMv7 is currently the latest version), while the ARM9 you are talking about is a core that implements the ARMv5 instruction set. See http://en.wikipedia.org/wiki/ARM_architecture#ARM_cores [wikipedia.org] for a list of ARM cores and the corresponding architecture version they implement.

  • With only two processing units, you'd have no CENTRAL processing unit, duh!

  • Blackberry will be announcing [engadget.com] a new tablet supposedly powered by a Marvell chip. Looks like we might see this chip in action soon enough.
  • Wait, didn't NEC do the same thing six years ago? http://www.physorg.com/news1344.html [physorg.com]
  • If I was a phone designer, reading this I would assume that I can install a realtime OS on the third core to perform phone and system management related functions, and use the other 2 cores for the user OS to run the UI and all the apps. With a well developed system, these are the features this chip could allow: - the user OS could reboot/freeze/crash and you can still make calls or stay on the line with the current call. - you could be down to the last couple of minutes of battery life, and decide to shu

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