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AMD Upgrades Hardware

AMD Details Upcoming Bulldozer Architecture 234

Posted by CmdrTaco
from the summon-bob-the-builder dept.
Vigile writes "AMD is taking the lid off quite a bit of information on its upcoming CPU architecture known as Bulldozer that is the first complete redesign over current processors. AMD's lineup has been relatively stagnant while Intel continued to innovate with Nehalem and Sandy Bridge (due late this year) and the Bulldozer refresh is badly needed to keep in step. The integrated north bridge, on-die memory controller and large shared L3 cache remain key components from the Athlon/Phenom generation to Bulldozer but AMD is adding features like dual-thread support per core (but with a unique implementation utilizing separate execution units for each thread), support for 256-bit SIMD operations (for upcoming AVX support) all running on GlobalFoundries 32nm SOI process technology."
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AMD Details Upcoming Bulldozer Architecture

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  • Re:Sweeeeet nectar (Score:3, Informative)

    by Cornelius the Great (555189) on Tuesday August 24, 2010 @12:25PM (#33357840)
    No pricing nor benchmarks. The article is purely a discussion about the architecture.
  • by kg8484 (1755554) on Tuesday August 24, 2010 @12:25PM (#33357852)

    Compared to such articles as AnandTech's [anandtech.com] coverage of this in November 2009, I don't see much new information. Perhaps the key bit, and this is glossed over but you can tell from the slides AMD gave them, is the difference between the bulldozer and bobcat cores. The bulldozer cores contain the two integer units that have been revealed before, but the bobcat core only has one but it still implements hyperthreading.

  • Re:AMD's stagnant? (Score:3, Informative)

    by SQL Error (16383) on Tuesday August 24, 2010 @12:37PM (#33358012)

    AMD are selling six-core dual-socket CPUs for $200 [acmemicro.com] now. They're not quite as fast as the Xeon 5500/5600, but the price/performance is awesome.

  • by WiglyWorm (1139035) on Tuesday August 24, 2010 @12:38PM (#33358026) Homepage
    It will be drop in compatable with AMD server boards. At home, it will be AM3+.
  • Re:AMD's stagnant? (Score:5, Informative)

    by blair1q (305137) on Tuesday August 24, 2010 @12:45PM (#33358168) Journal

    "AMD's lineup has been relatively stagnant while Intel continued to innovate with Nehalem and Sandy Bridge (due late this year) and the Bulldozer refresh is badly needed to keep in step."

    Likely another Intel fanboy trying to spread FUD about the company that he doesn't like and at the same time getting his username posted on the front page.

    The facts in that quote were presented clearly. AMD is a generation behind on architecture, trying to get comparable performance by multiplying old cores, while Intel has been advancing architecture and multiplying cores at the same time. For about 4 years now, Intel has had 2-4 chips performing at levels above anything AMD could produce.

    It remains to be seen if Bulldozer will put AMD anywhere near at-par on a performance/core basis, but it's not 2002 any more, and AMD has no hope of a performance lead.

  • Re:AMD's stagnant? (Score:4, Informative)

    by ArcherB (796902) on Tuesday August 24, 2010 @01:19PM (#33358766) Journal

    Intel's hexacore offering features hyperthreading technology, which allows each core to execute two threads simultaneously. This means that Intel's hexacore chips actually have twelve logical cores, while the AMD hexacore chips only have six logical cores.

    I think you may be misunderstanding what hyperthreading is. A processor (or core) can only execute one instruction at a time, hyperthreading or not. All hyperthreading does is allow for two sets of instructions to be queued up, so if one thread (or queue) gets hung up for whatever reason, like waiting over a cache miss, the other instructional thread can proceed, rather than patiently waiting in line.

    Think of it as one of those tumbling thingies you have to pass through to get into Six Flags or the subway. It's like that, but hyperthreading has two lines instead of one. If one moron has to stop to find his ticket at the front of the line, the other line may move until he finds it.

    Your number of physical cores comparison is meaningless...

    Um... no. I believe your "virtual" core comparison is meaningless. I'll take a quad core anything over a dual core hyperthreaded-anything-else any day, thank you. Virtual cores don't mean shit until a thread stalls.

    and actual performance benchmarks show that the Core i7 980X is more than twice as fast as the AMD Phenom II X6 1055T. [1]

    From the site you linked:

    Intel Core i7 980X @ 3.33GHz: Score of 10,325 at $989.99*
    AMD Phenom II X6 1055T: Score of 5,146 at $194.99*

    Hmmmm... Twice the performance at over 5x the cost. Strange, I don't know why you chose that AMD chip. It's odd that you would choose the fastest Intel chip and a middle of the road AMD Chip. Why not this one?
    AMD Phenom II X6 1090T: Score of 6,057 at $289.99*.

    Oh, I know. Thenyou wouldn't be able to use the 2x faster line. I get it now.

    Here, take a look at THIS [cpubenchmark.net] chart and pay attention to the price/performace graph. You'll see that your chip performs about 2.5x less than the AMD Phenom II X5 965 when price is a consideration. Oh, and for nearly everyone that is not living off their mommy's credit cards, price is a consideration.

  • by Rockoon (1252108) on Tuesday August 24, 2010 @01:23PM (#33358846)
    Just to be clear, when you say "integer units" you mean "integer schedulers" and not actual integer execution units, of which even the old Athlon's had 3 per core (and that hasnt changed since then.)

    Unlike Intel design, with highly asymmetric execution units, AMD's have had 3 symmetric integer execution units per core since the original Athlons. Its actually a pleasant breeze to write hand-optimized integer code on AMD's.

    This new design looks (in the diagram) like it actually has 4 symmetric integer execution units per integer scheduler, with the bulldozer having 2 schedulers per core while the bobcat only having 1 per core (I would guess that the logical cores are alternated on rise-and-fall states of the clock on the bobcat, and the diagram certainly makes it look like that is the case.)

    Each seem to have two wide floating point execution units, so the floating point performance of both bulldozers and bobcat's are probably equivalent.

    What I think AMD has done here is that with the bulldozer, in integer performance it is going to behave like it has 2x the number of real cores. So an 8 core (16 thread) chip will perform much like an 8 core CPU in floatng point work, but much more like a true 16-core CPU in integer work. This should give it a large advantage over Intel in integer work in equal-core comparisons, but the floating point performance will still lag behind Intel.
  • Re:Mmm (Score:3, Informative)

    by coredog64 (1001648) on Tuesday August 24, 2010 @02:42PM (#33360128)

    Development on what became the IA64 started in 1989 by HP and Intel was brought in in 1994 and the first implementation was in 1998 - hell it is the reason we don't see Alpha's anymore.

    The reason we don't see Alpha anymore is that Intel coerced HP to buy up Compaq and kill it off by offering to assist HP in porting HP-UX to Itanic.

  • by Rockoon (1252108) on Tuesday August 24, 2010 @03:12PM (#33360578)

    I was never a big fan of the 3x symmetric ALU's in the Athlons. When it comes to integer intensive code, having a ton of independent ADDs or MULs that I'd need that kind of parallelism for was rare. And the latency (compared to a sane design like Core at least) were significantly higher due to the units being multi-purpose.

    In the Phenom II design the latency of most of the register to register integer instructions is exactly 1 cycle just like the i7. The units being multi-purpose is not a latency sacrifice at all, although maybe the original Athlons had poor latency for another reason and Agner Fog's reference actually indicates that most of the register to register integer instructions on even the early K7's also had 1 cycle latency.

    Even in mem,reg operations, the Phenom II beats out the I7 in latency on many operations (ex: xor [ebx], eax .. 6 cycle latency on i7, 4 cycle latency on Phenom II) .. where the I7 really shines the most is in reading directly from L1 into registers (2 cycle latency vs 3 cycle latency), with a massive 50% advantage on one of the most common operations..

  • by blair1q (305137) on Tuesday August 24, 2010 @05:19PM (#33362588) Journal

    If you're running any Windows since XP, you're using all of your cores all the time, and it's benefitting you. You may not get all of them working on the same task, but the fact that the other cores can do background and response tasks while your foreground task pegs one of the cores is always a bonus. If it doesn't show up in outright speed of completion, it hides a vast array of niggling little delays that make things jerky.

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