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Toshiba To Test Sub-25nm NAND Flash 80

Posted by CmdrTaco
from the who-wants-underwater-memory dept.
An anonymous reader writes "Toshiba plans to spend about $159.8 million this year to build a test production line for NAND flash memory chips of less than 25 nanometers. The company hopes to kick off mass production of the chip as early as 2012. The fabrication facility for this key NAND flash memory will be located at Yokkaichi, Mie Prefecture."
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Toshiba To Test Sub-25nm NAND Flash

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  • ultimate limit (Score:5, Interesting)

    by goombah99 (560566) on Monday April 05, 2010 @10:52AM (#31733866)

    Is there a proposed ultimate limit for lithography before one has to jump to molecular electronics? 25nm is well below what anyone though practical a decade ago (since it's so many times smaller than easily produced optical wavelengths). Now it's closing in on the limit of easily produced x-rays.

    while the resolution of the smallest resolvable element is shrinking, is the utilization of area increasing proportionally. That is are we densely filling the area with 25nm structures or is that simply the finest linear element and these are well separated?

    A 1cm chip would have 1E15 resolvable points at 0.025 micron resolution. And then there is the vertical resolution to multiply that. I should think it would become prohibitively difficult to design something with so many possibilities.

  • Re:ultimate limit (Score:3, Interesting)

    by vlm (69642) on Monday April 05, 2010 @11:36AM (#31734474)

    Hmm. Well, Si unit cell spacing is about 0.5 nm and graphene C-C spacing is about 0.15 nm. The longest diagonal of a hexagon is twice one side, so the minimal graphene unit cell lattice would be about 0.30 nm.

    So, for all the trouble of scrapping an entire industry and starting over, we'd only go from 0.50 to 0.30 nm. Not sure if thats going to be worth it.

    Not that graphene isn't interesting or cool, just that its unit cell isn't much smaller than Si unit cell.

  • Re:NAND? (Score:3, Interesting)

    by AdamHaun (43173) on Monday April 05, 2010 @02:13PM (#31737370) Journal

    No, it has little to do with the NAND digital logic gate -- the other person who responded to you is totally wrong. NAND flash is a circuit topology where the flash transistors (bits) are arranged in long series chains, like this:

    http://commons.wikimedia.org/wiki/File:Nand_flash_structure.svg [wikimedia.org]

    which is similar to the pull-down side of a NAND gate. NAND flash is very high-density but is read in blocks (you turn on the whole chain and then check one bit at a time). The other type of flash is NOR flash, which uses transistors in parallel:

    http://commons.wikimedia.org/wiki/File:NOR_flash_layout.svg [wikimedia.org]

    This means you can read any bit individually without having to turn the others on. NOR flash is commonly used for program memory in microcontrollers, where you need fast random access to any bit. NAND flash is used when you need high capacity, as in memory cards or SSDs.

  • by marcansoft (727665) <hector@mar c a nsoft.com> on Monday April 05, 2010 @05:43PM (#31741532) Homepage

    MLC NAND Flash is already horribly unreliable. Manufacturers don't care about errors, quantum or not. The proper question to ask is when will quantum effects become dominant such that decreasing feature size loses more memory from failure than you gain from the reduced size. Until then, people will just slap on better ECC and nobody cares if a large number of bits are randomly flipping.

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