Toshiba To Test Sub-25nm NAND Flash 80
An anonymous reader writes "Toshiba plans to spend about $159.8 million this year to build a test production line for NAND flash memory chips of less than 25 nanometers. The company hopes to kick off mass production of the chip as early as 2012. The fabrication facility for this key NAND flash memory will be located at Yokkaichi, Mie Prefecture."
You forgot the "so what". (Score:5, Insightful)
Re:You forgot the "so what". (Score:2, Insightful)
The smaller the transistors, the more that can be packed into a smaller area. Basically, this will allow you to have smaller chips that will have denser memory capacities. The benefits come into things like phones, tablet PC's, netbooks, cameras, cars, computers, etc. Anything that uses or can use digital memory will benefit from smaller components.
It'll also decrease the price for components out now, and that's always nice.
I just wonder what'll happen when we hit the quantum wall -- the point at which quantum effects become apparent and electronics behave erratically.
Re:When does it stop? (Score:3, Insightful)
*tronics
Chemitronics? Quantatronics? What does this mean?!?!?
What would this mean for the consumer? (Score:3, Insightful)
Personally, while I find it interesting, I'd like to know just how much extra data storage this would enable?
32nm to 25 nm would, what, increase the theoretical max density of flash by 64%? IE instead of getting a 16GB chip you'd get a 24GB one.
At the same price once you have all the details worked out, of course.
45nm to 25 nm by my figuring would allow 3.24 times as much storage in a given size of chip.
Details? (Score:3, Insightful)
The article is frustratingly light on details. There's nothing about what type of flash transistor they're using (there are several variants on the basic stacked-gate NMOS design as well as more wild types). They don't say whether they're actually shrinking the bits (which you don't have to do) or just the support circuitry. All it says is that Toshiba is making NAND flash in a new process node, probably 22nm.
My day job is working with embedded NOR flash. I'm not really a process or solid state physics guy, but I think I know enough to comment, unlike a lot of the people running their mouths. (Seriously, folks, if you don't know what you're talking about, *shut up*. Misinforming people with wild guesses is not helpful, no matter how much it strokes your ego.)
First off, the flash transistor itself is not 22nm long. It's probably at least ten times longer, if not more (obviously Toshiba's not giving exact numbers). When you go to a new process node you don't necessarily shrink every feature by 50%. The limiting factor in flash size isn't lithography (manufacturing), it's leakage.
Flash works by storing electrons on an isolated (floating) material sandwiched inside an NMOS transistor [linux-mag.com]. If extra electrons are present, the transistor is forced off (0). If they aren't, the transistor can turn on (1). The problem is that over time the electrons leak out of the floating gate, eventually causing bits to flip. If you shrink the circuit enough you hit a point where you can't keep electrons in the gate for a reasonable amount of time. At that point, we'll need a new memory technology -- maybe FRAM [wikipedia.org], maybe something else. Whatever it is, I'm sure it's been researched already -- a lot of the major research papers for flash memory are 25+ years old.
Also, I said this elsewhere, but NAND flash is called NAND because the flash transistors (bits) are in series, like the NMOS transistors in a NAND gate. It isn't made out of logic gates or anything like that. Flash memory is analog, like DRAM -- you need special analog circuitry to read it and output a digital signal.