Toshiba To Test Sub-25nm NAND Flash 80
An anonymous reader writes "Toshiba plans to spend about $159.8 million this year to build a test production line for NAND flash memory chips of less than 25 nanometers. The company hopes to kick off mass production of the chip as early as 2012. The fabrication facility for this key NAND flash memory will be located at Yokkaichi, Mie Prefecture."
Re:Marginal Gain? (Score:2, Informative)
Well, chips are 2D, so you also get to square that benefit.
32x32 = 1024 nm^2
25x25 = 625 nm^2
That's nearly 18 months of Moore's Law right there.
Re:You forgot the "so what". (Score:5, Informative)
Re:You forgot the "so what". (Score:4, Informative)
witch means an approx 4 x larger yield on a 300mm wafer
I'm not sure what witches have to do with it, but the yield improvement from a process shrink is more than just the 4x that you get from cramming four times as many chips on a wafer. An impurity in the wafer typically destroys one die. If you're unlucky it may be between 2 or even 4. If you make each die smaller then an impurity of the same size may only destroy 1-3 of the 4 in the same area as one of the originals.
Re:ultimate limit (Score:3, Informative)
Re:You forgot the "so what". (Score:3, Informative)
Shrinking a process gives several benefits, but a quick general overview helps:
Silicon as used in chip manufacturing is expensive. It costs a lot to grow, cut and polish. It's also a mature industry, so no real breakthroughs are likely to happen to reduce the cost of the silicon. The less silicon area you use, the more chips you can make for the same cost. Next is manufacturing. Whether you put one transistor per square millimeter or 100,000 per square millimeter, the cost is the same, or at least within a penny. Coat, expose to a masked pattern, etch, sputter, clean and repeat a few times, and voila, you have a chip. Shining a light through a mask costs the same no matter the resolution of the mask. Dunking the wafer in a chemical etch bath is the same, running a wafer through a sputterer or CVD costs the same, etc. Labor costs are basically per wafer, so more components per wafer means you get more output for the same labor (and plant infrastructure) dollar.
So, a smaller manufacturing process means:
More components per wafer. Thus if you double the component density, your manufacturing costs will remain the same, and you can double output while keeping costs the same (think 32GB for the price of 16GB).
You can also make the chips smaller while keeping the same capacity (same 16GB chip uses half the silicon, thus costs 50% less to make, think 16GB for half the cost you paid last year).
Or, more capacity within given size limits. (think 64GB or 128GB SD cards, or 2 TB Compact Flash).
A litho primer (Score:2, Informative)
The official roadmap for processes and feature sizes (called process nodes) are published yearly by the International Technology Roadmap for Semiconductors, a consortium of all the fabs. According to the 2009 lithography report [itrs.net]. 25nm Flash is supposed to hit full production in 2012, thus inital deployments happen a couple of years before. Effectively Toshiba seems to be hitting the roadmap.
The takeaway being, theres nothing to see here, its progress as usual. The big problem is what happens under 16nm. Thats the point at which current optical lithography is impossible, even using half or quarter wavelength, and EUV with immersion litho.