Toshiba To Test Sub-25nm NAND Flash 80
An anonymous reader writes "Toshiba plans to spend about $159.8 million this year to build a test production line for NAND flash memory chips of less than 25 nanometers. The company hopes to kick off mass production of the chip as early as 2012. The fabrication facility for this key NAND flash memory will be located at Yokkaichi, Mie Prefecture."
microSD (Score:3, Funny)
I thought microSD was small. I'm going to lose this stuff for sure!
Re:microSD (Score:2, Funny)
Re:microSD (Score:1)
Re:microSD (Score:0)
Yayyyyyyyy! I bought a couple of USB sticks and stuck them on the back of the computer a couple years ago. They are 4GB each, and I bought two because they were about half the price (for two) as a single 8GB stick. If they are making the feature size of these smaller, then they can surely stuff more capacity into an identical sized space. It isn't nearly as fast as getting data off the hard disk, but when you need to move a lot of stuff, or when the disk crashes, its nice to have a physical backup (slow is better than typing everything in again, or worse, losing it forever). I don't advocate doing system backups on 64GB or 128 GB usb sticks, mostly because data transfer speeds are relatively slow, and the amount you can store is less than a single drive, or multiple drives. But, in the case of business intelligence, you can store at least the critical applications and critical data on these, and lock them in a box offsite, and when the walls come tumbling down, get back to some semblance of normal more quickly. Oh, and they are in general, quite reliable.
1st post (Score:-1, Offtopic)
that's it.
You forgot the "so what". (Score:5, Insightful)
Re:You forgot the "so what". (Score:2, Insightful)
The smaller the transistors, the more that can be packed into a smaller area. Basically, this will allow you to have smaller chips that will have denser memory capacities. The benefits come into things like phones, tablet PC's, netbooks, cameras, cars, computers, etc. Anything that uses or can use digital memory will benefit from smaller components.
It'll also decrease the price for components out now, and that's always nice.
I just wonder what'll happen when we hit the quantum wall -- the point at which quantum effects become apparent and electronics behave erratically.
Re:You forgot the "so what". (Score:1)
Re:You forgot the "so what". (Score:1)
True. I'm expecting reduced functionality that will eliminate the possible benefits from this size. I remember reading that it was sub 45 nm that the effects became apparent, but I'm not entirely sure.
Re:You forgot the "so what". (Score:3, Interesting)
MLC NAND Flash is already horribly unreliable. Manufacturers don't care about errors, quantum or not. The proper question to ask is when will quantum effects become dominant such that decreasing feature size loses more memory from failure than you gain from the reduced size. Until then, people will just slap on better ECC and nobody cares if a large number of bits are randomly flipping.
Re:You forgot the "so what". (Score:2)
The first example would give bigger capacity and the second lower prices. Besides that there are benefits on power usage and read/write speeds.
From TFA some flash already use a 32nm process, so the gain would not be so big compared to those (I'll let you do the math), unless they are talking about 16nm. That is doubtful, as 16nm is very much "sub 25nm" - and they would want to advertise that fact.
Re:You forgot the "so what". (Score:4, Informative)
witch means an approx 4 x larger yield on a 300mm wafer
I'm not sure what witches have to do with it, but the yield improvement from a process shrink is more than just the 4x that you get from cramming four times as many chips on a wafer. An impurity in the wafer typically destroys one die. If you're unlucky it may be between 2 or even 4. If you make each die smaller then an impurity of the same size may only destroy 1-3 of the 4 in the same area as one of the originals.
Re:You forgot the "so what". (Score:2)
I would have thought that an impurity/defect of the same size would be more likely to destroy more chips if the chips are smaller - esp if the defect is big. If the defect is really small it's unlikely to damage more than one chip in which case see below:
To me a more plausible reason is if each chip is smaller, you get more chips per wafer. So assuming the same number of tiny defects scattered across the wafer, you'd have more good chips per wafer - since 8 bad chips out of 100 is better than 8 bad chips out of 25. The first one = 92 good chips, the second one = 17. Which is more than 4 x.
Of course what Intel et all do is they also make the chips able to still work if some portions are defective - so the chip gets sold with less cache, and/or fewer cores.
Re:You forgot the "so what". (Score:2)
Most NAND Flash chips are already defective - it's just that the defects are branded "factory bad blocks" and the chips get sold anyway. We're well past the point where 100% reliability is possible and well into the realm of using error correction and flash translation layers to mask an increasingly poor memory array.
Re:You forgot the "so what". (Score:2)
I would have thought that an impurity/defect of the same size would be more likely to destroy more chips if the chips are smaller - esp if the defect is big. If the defect is really small it's unlikely to damage more than one chip in which case see below:
Yes, more of the chips are defective, but a smaller fraction of them are. Consider a wafer with one chip. Anywhere you put a defect, it destroys one chip, and the yield is 0%. Now make the wafer into 4 chips and put the same small defect somewhere. Most likely, it will hit just one chip, but it may overlap a border between two, so you get two dead chips but the yield is now 50%. Now make it hold 9 chips. They're smaller, so the defect now destroys 4 of them, but the yield is 55%.
Re:You forgot the "so what". (Score:5, Informative)
Re:You forgot the "so what". (Score:2)
Simple. Moore's Law. The number of transistors double every 18 months (roughly).
The benefit? What device you use where the number of transistors directly affects you? Memory cards primarily - things like CPUs and GPUs and chipsets, not so much (most of the space is taken up with wires). But a 32GB card has over 16 billion transistors in it. Now we double that in 18 months, and that same card can have 64GB of data, or effectively the same cost.
Maybe the card you use in your digital camera isn't too exciting. But if you wanted a decent sized SSD, it means once the next node is mature, SSD prices effectively tumble by half, so that 128GB SSD you were eyeing at $500 suddenly costs $250. Or that stratospheric 256GB SSD drops to something that a little saving can pay for.
Of course, hard drives don't obey Moore's Law, and their increase in capacity is somewhat faster, making the spinning media-SSD gap even bigger.
Re:You forgot the "so what". (Score:3, Informative)
Shrinking a process gives several benefits, but a quick general overview helps:
Silicon as used in chip manufacturing is expensive. It costs a lot to grow, cut and polish. It's also a mature industry, so no real breakthroughs are likely to happen to reduce the cost of the silicon. The less silicon area you use, the more chips you can make for the same cost. Next is manufacturing. Whether you put one transistor per square millimeter or 100,000 per square millimeter, the cost is the same, or at least within a penny. Coat, expose to a masked pattern, etch, sputter, clean and repeat a few times, and voila, you have a chip. Shining a light through a mask costs the same no matter the resolution of the mask. Dunking the wafer in a chemical etch bath is the same, running a wafer through a sputterer or CVD costs the same, etc. Labor costs are basically per wafer, so more components per wafer means you get more output for the same labor (and plant infrastructure) dollar.
So, a smaller manufacturing process means:
More components per wafer. Thus if you double the component density, your manufacturing costs will remain the same, and you can double output while keeping costs the same (think 32GB for the price of 16GB).
You can also make the chips smaller while keeping the same capacity (same 16GB chip uses half the silicon, thus costs 50% less to make, think 16GB for half the cost you paid last year).
Or, more capacity within given size limits. (think 64GB or 128GB SD cards, or 2 TB Compact Flash).
Addition: Blemishes / Question (Score:2)
Imperfect silicon wafers tend to have little dot-like blemishes. So there are points on wafers which spoil the chip that gets printed at that point.
As chips get smaller, more chips get printed on a wafer, but the count of blemishes (and thus spoiled chips) stays the same -- so as a percentage of chips on wafer, manufacturing reliability goes up.
One chip on a wafer with a blemish -- complete loss. .1% loss.
Two chips, one blemish -- 50% loss.
1000 chips, one blemish --
So smaller chips mean lower manufacturing costs, there, too.
HOWEVER, I suspect someone on this thread can tell us if the smaller wavelength process (25nm, here) causes imperfections which would otherwise have allowed the chip to work fine to become an important blemish.
Will chip failure count go up because of this new process?
Re:You forgot the "so what". (Score:2)
Re:You forgot the "so what". (Score:2)
Relevant: XKCD: "MicroSD" [xkcd.com]
Kinda scary to think about having that much data in just one tiny flash card. Really need a faster way to dupe 'em.
-l
/Just sent in an A-Data card for warranty support. Le sigh.
Re:You forgot the "so what". (Score:2)
Comment removed (Score:2)
Marginal Gain? (Score:2)
Re:Marginal Gain? (Score:2, Informative)
Well, chips are 2D, so you also get to square that benefit.
32x32 = 1024 nm^2
25x25 = 625 nm^2
That's nearly 18 months of Moore's Law right there.
Re:Marginal Gain? (Score:2)
You mean to tell me the 3D chip in my computer is actually 2D?
What a rip-off!
Re:Marginal Gain? (Score:2)
Re:Marginal Gain? (Score:2)
Re:Marginal Gain? (Score:2)
So it's more like 2.5D, I still feel ripped off!
I suggest not watching Fury of Titans on a 3D cinema, then.
Re:Marginal Gain? (Score:0)
It means only 72% of the power, or 140% of the storage.
Re:Marginal Gain? (Score:2)
Toshiba again? (Score:0)
When does it stop? (Score:3, Funny)
For those in the know, this ever shrinking manufacturing process tech: when will it stop? Where will it stop? 10nm? Sub-1nm?
Re:When does it stop? (Score:0)
Doing better than single molecules going to require an even more serious paradigm shift (better parallelization? quantum computing?)... Computers may continue getting better, but it won't be micronization as the driving force.
Re:When does it stop? (Score:2)
For those in the know, this ever shrinking manufacturing process tech: when will it stop?
Probably never. The walls always come down.
Re:When does it stop? (Score:1)
Re:When does it stop? (Score:2)
And yet someone has made a transistor out of three molecules. The silicon wall will come down as well; something will be developed to take its place, and be better, cheaper, smaller, and use less power. Progress has slowed at times and even gone backwards at times, but for the most part progress hasn't stopped since the invention of the stone tool.
Re:When does it stop? (Score:2)
Well, there’s always the Planck length [wikipedia.org], as as the ultimate size limitation. As there need to be some structures, it always have to be a multiple of that.
But everything else depends on of we can overcome the difficulties of constructing working *tronics out of structures that small.
Re:When does it stop? (Score:3, Insightful)
*tronics
Chemitronics? Quantatronics? What does this mean?!?!?
Re:When does it stop? (Score:2)
electronics, positronics, quantumtronics... Or maybe it's like "Trekkies," but for fans of Tron?
Re:When does it stop? (Score:2)
Well, there's always the Planck length, as as the ultimate size limitation.
Unless we find out a way of storing stuff on a place directly accesible but not physically close in 3d space. Either by new means of comunication or by new means of accessing an additional dimension.
Re:When does it stop? (Score:2)
Well, there’s always the Planck length [wikipedia.org], as as the ultimate size limitation. As there need to be some structures, it always have to be a multiple of that.
But everything else depends on of we can overcome the difficulties of constructing working *tronics out of structures that small.
The Planck length? that's like 25 orders of magnitude smaller then what we are looking at now. I'd be surprised if there is a way to scale below the width of a single walled nano tube(~1nm)
Re:When does it stop? (Score:0)
The roadmap for chip feature sizes is set by ITRS, and manufacturers generally try to at least follow (and hopefully outpace) it. Currently it says that flash chips will be at 6.3nm in 2024, and that's its furthest prediction. If I recall correctly, the ability of electrons to quantum tunnel through the channel of transistors will become a serious issue around 5nm. So there will definitely have to be some changes in the process before then.
Re:When does it stop? (Score:1)
Re:When does it stop? (Score:2)
For those in the know, this ever shrinking manufacturing process tech: when will it stop? Where will it stop? 10nm? Sub-1nm?
Well, if the lattice spacing of a silicon crystal is a bit more than 1/2 a nm, I think it unlikely we'd have a silicon crystal process much smaller than the smallest unit crystal of silicon.
http://en.wikipedia.org/wiki/Silicon#Crystallization [wikipedia.org]
Its interesting that a 25nm process means parts are only about 50 atoms across. So, one individual contaminant atom means about a 2% change in composition, probably resulting in much more than 2% change in electrical properties. So the design has to be pretty fault tolerant, or cleanliness must be amazing, or yields must be pretty low, or all of the above of course.
Re:When does it stop? (Score:2)
For those in the know, this ever shrinking manufacturing process tech: when will it stop? Where will it stop? 10nm? Sub-1nm?
There is a hard physical limit based on the silicon and dopant distribution. On a macro scale, the silicon is very homogenous. However once you get a feature size down to the point where it encompasses only a few hundred atoms on a side, you begin to run into the real possibility that such small localised areas are over- or under-doped. Thus you have a new source of potential defects because your charge carriers are overabundant or underabundant. We've been solving the diffraction problem nicely to the point where we can project ever-smaller patterns onto the wafers, but eventually there will come a point of diminishing returns when defect rate increases negate any benefit gained from feature size shrinks.
Re:When does it stop? (Score:1)
Re:When does it stop? (Score:2)
I believe around 8 nm electron tunneling becomes a serious issue. At that point the electrons will "tunnel" between transistors even if there was infinite resistance in between the two transistors. This happens at larger distances as well, but not too often.
Re:When does it stop? (Score:2)
It's not going to just stop! Pretty soon it's going to reverse! And then we'll design our chips in 3D! Blessed 130nm 3D!
(this was part joke, part serious - most modern chips are very complicated, but flat...)
Re:When does it stop? (Score:0)
Silicon crystal is spaced at about 2 molecules per nm. The manufacturers claim that there's a clear path all the way to 10nm (20 molecules) and they have ideas that might work beyond that in the pipeline.
ultimate limit (Score:5, Interesting)
Is there a proposed ultimate limit for lithography before one has to jump to molecular electronics? 25nm is well below what anyone though practical a decade ago (since it's so many times smaller than easily produced optical wavelengths). Now it's closing in on the limit of easily produced x-rays.
while the resolution of the smallest resolvable element is shrinking, is the utilization of area increasing proportionally. That is are we densely filling the area with 25nm structures or is that simply the finest linear element and these are well separated?
A 1cm chip would have 1E15 resolvable points at 0.025 micron resolution. And then there is the vertical resolution to multiply that. I should think it would become prohibitively difficult to design something with so many possibilities.
Re:ultimate limit (Score:2)
oops my bad: 1.6E11 resolvable points on a 1cm chip. still a lot to design for.
Re:ultimate limit (Score:2)
I think once it's too hard to squeeze more things into a 2D surface we might start seeing development into 3D space.
And then it leads to the creation of Skynet, etc... very bad stuff.
Re:ultimate limit (Score:3, Informative)
Re:ultimate limit (Score:3, Interesting)
Hmm. Well, Si unit cell spacing is about 0.5 nm and graphene C-C spacing is about 0.15 nm. The longest diagonal of a hexagon is twice one side, so the minimal graphene unit cell lattice would be about 0.30 nm.
So, for all the trouble of scrapping an entire industry and starting over, we'd only go from 0.50 to 0.30 nm. Not sure if thats going to be worth it.
Not that graphene isn't interesting or cool, just that its unit cell isn't much smaller than Si unit cell.
Re:ultimate limit (Score:2)
no, it isn't, but isn't part of the point of graphene being able to jack higher voltages through it, thus achieving higher speeds before the wall's hit there? If we can continue to make something smaller, even if only a tiny bit (heh), but can jack up clock speeds and such, then it's still a good improvement, though less useful for SSD-type use.
Re:ultimate limit (Score:1)
So, for all the trouble of scrapping an entire industry and starting over, we'd only go from 0.50 to 0.30 nm. Not sure if thats going to be worth it. Not that graphene isn't interesting or cool, just that its unit cell isn't much smaller than Si unit cell.
It's not about scaling, the key property of graphene is greatly improved electron mobility. It also has many other interesting properties.
Re:ultimate limit (Score:1)
Re:ultimate limit (Score:2)
If that was an answer, then what was the question?
Assuming the question was something like "how will we get to sub-22nm technologies", I'll one-up you: Extreme Ultraviolet. (Wavelength - 13.5nm vs. ArF with pitch-doubling which would be equivalent of 193/2=96.5nm, so a factor of about seven better. ) Lately, the prospects for EUV have been getting pushed out to later years, but nothing new there.
Re:ultimate limit (Score:2)
Re:ultimate limit (Score:0)
I should think it would become prohibitively difficult to design something with so many possibilities.
Naa.
Molecular? (Score:2)
Even in poorly funded labs for well over a decade people have been getting down to atomic scales where a single layer of another element can give a junction. The materials can do it but the problem is fabricating it.
NAND? (Score:1)
Re:NAND? (Score:1)
Re:NAND? (Score:1)
Re:NAND? (Score:2)
Re:NAND? (Score:3, Interesting)
No, it has little to do with the NAND digital logic gate -- the other person who responded to you is totally wrong. NAND flash is a circuit topology where the flash transistors (bits) are arranged in long series chains, like this:
http://commons.wikimedia.org/wiki/File:Nand_flash_structure.svg [wikimedia.org]
which is similar to the pull-down side of a NAND gate. NAND flash is very high-density but is read in blocks (you turn on the whole chain and then check one bit at a time). The other type of flash is NOR flash, which uses transistors in parallel:
http://commons.wikimedia.org/wiki/File:NOR_flash_layout.svg [wikimedia.org]
This means you can read any bit individually without having to turn the others on. NOR flash is commonly used for program memory in microcontrollers, where you need fast random access to any bit. NAND flash is used when you need high capacity, as in memory cards or SSDs.
Cheaper SSD? (Score:1)
"About 159.8M"? (Score:1)
4SF is pretty accurate for an 'about'. Why not 'About $160M".
Re:"About 159.8M"? (Score:2)
Scientists and engineers love them some sig figs. Since precision would be nine sig figs, anything less is an about, to them. ;)
What would this mean for the consumer? (Score:3, Insightful)
Personally, while I find it interesting, I'd like to know just how much extra data storage this would enable?
32nm to 25 nm would, what, increase the theoretical max density of flash by 64%? IE instead of getting a 16GB chip you'd get a 24GB one.
At the same price once you have all the details worked out, of course.
45nm to 25 nm by my figuring would allow 3.24 times as much storage in a given size of chip.
Hey! I'm getting this implanted in my wrist (Score:1)
Re:What would this mean for the consumer? (Score:2)
New Lithography Wavelength? (Score:1)
A litho primer (Score:2, Informative)
The official roadmap for processes and feature sizes (called process nodes) are published yearly by the International Technology Roadmap for Semiconductors, a consortium of all the fabs. According to the 2009 lithography report [itrs.net]. 25nm Flash is supposed to hit full production in 2012, thus inital deployments happen a couple of years before. Effectively Toshiba seems to be hitting the roadmap.
The takeaway being, theres nothing to see here, its progress as usual. The big problem is what happens under 16nm. Thats the point at which current optical lithography is impossible, even using half or quarter wavelength, and EUV with immersion litho.
Re:A litho primer (Score:1)
IIRC, lithos down to 13nm are believed to be possible. NAND will start hitting terminal reliability problems below 20nm as the floating gates will likely hold 100 electrons (or less!) and far more susceptible to random drainage and bit errors way beyond what is currently experienced.
So we'll end up with more, higher-density, and fundamentally unstable nonvolatile memory. As I understand it, DRAM will be hitting this problem too, as the capacitors will become susceptible to spontaneous charge loss.
Re:A litho primer (Score:2)
The takeaway being, theres nothing to see here, its progress as usual. The big problem is what happens under 16nm. Thats the point at which current optical lithography is impossible, even using half or quarter wavelength, and EUV with immersion litho.
So, around 1/2 of what this factory will produce? That would translate, in a perfect world, to around 4X of what the 25nm process would create.
Call it 16X the storage per area of current processes.
Given that SSDs are STILL something like 100X the price per gigabyte than hard drives, will we ever see the end of the spinning platter?
Matter of fact, I'll jinx myself here:
I'm afraid that we're going to see a plateuing of storage capabilities within my lifetime. One guy I was talking with was convinced that hard drives have almost reached their economical max density, while convinced that flash would surpass them in five years. Personally, I placed it more like 10-15, but with concerns about just how small they could go with the process. I figured we'd have more room, personally.
Re:A litho primer (Score:1)
The big problem is what happens under 16nm.
Maybe 3D chip stacking [ibm.com] will help prolong Moore's law for a while, instead of further miniaturization.
Micron and Intel Previously Announced Production (Score:1)
Details? (Score:3, Insightful)
The article is frustratingly light on details. There's nothing about what type of flash transistor they're using (there are several variants on the basic stacked-gate NMOS design as well as more wild types). They don't say whether they're actually shrinking the bits (which you don't have to do) or just the support circuitry. All it says is that Toshiba is making NAND flash in a new process node, probably 22nm.
My day job is working with embedded NOR flash. I'm not really a process or solid state physics guy, but I think I know enough to comment, unlike a lot of the people running their mouths. (Seriously, folks, if you don't know what you're talking about, *shut up*. Misinforming people with wild guesses is not helpful, no matter how much it strokes your ego.)
First off, the flash transistor itself is not 22nm long. It's probably at least ten times longer, if not more (obviously Toshiba's not giving exact numbers). When you go to a new process node you don't necessarily shrink every feature by 50%. The limiting factor in flash size isn't lithography (manufacturing), it's leakage.
Flash works by storing electrons on an isolated (floating) material sandwiched inside an NMOS transistor [linux-mag.com]. If extra electrons are present, the transistor is forced off (0). If they aren't, the transistor can turn on (1). The problem is that over time the electrons leak out of the floating gate, eventually causing bits to flip. If you shrink the circuit enough you hit a point where you can't keep electrons in the gate for a reasonable amount of time. At that point, we'll need a new memory technology -- maybe FRAM [wikipedia.org], maybe something else. Whatever it is, I'm sure it's been researched already -- a lot of the major research papers for flash memory are 25+ years old.
Also, I said this elsewhere, but NAND flash is called NAND because the flash transistors (bits) are in series, like the NMOS transistors in a NAND gate. It isn't made out of logic gates or anything like that. Flash memory is analog, like DRAM -- you need special analog circuitry to read it and output a digital signal.