Building a 32-Bit, One-Instruction Computer

Hugh Pickens writes "The advantages of RISC are well known — simplifying the CPU core by reducing the complexity of the instruction set allows faster speeds, more registers, and pipelining to provide the appearance of single-cycle execution. Al Williams writes in Dr Dobbs about taking RISC to its logical conclusion by designing a functional computer called One-Der with only a single simple instruction — a 32-bit Transfer Triggered Architecture (TTA) CPU that operates at roughly 10 MIPS. 'When I tell this story in person, people are usually squirming with the inevitable question: What's the one instruction?' writes Williams. 'It turns out there's several ways to construct a single instruction CPU, but the method I had stumbled on does everything via a move instruction (hence the name, "Transfer Triggered Architecture").' The CPU is implemented on a Field Programmable Gate Array (FPGA) device and the prototype works on a 'Spartan 3 Starter Board' with an XS3C1000 device available from Digilent that has the equivalent of about 1,000,000 logic gates, costing between $100 and $200. 'Applications that can benefit from custom instruction in hardware — things like digital signal processing, for example — are ideal for One-Der since you can implement parts of your algorithm in hardware and then easily integrate those parts with the CPU.'"

That instruction is ..........

[140Mandak262Jamuna]

-------------drum roll

0x2A

That is the ultimate instruction.

"ideal for One-Der"?

[mpoulton]

It seems specious to say that One-Der is optimal for a task because it offers the flexibility of the underlying FPGA hardware. If you have the FPGA hardware present to run the One-Der implementation, then you could just configure a more optimally designed processor out of it for whatever task you are actually performing.

nihilist

[Nadaka]

vaguely reminds me of the nihilist language joke. A language that realizes that ultimately all things are futile and irrelevant, thus allowing all instructions to be reduced to a no-op.

Cheating?

[happy_place]

So the one instuction is essentially a move command that has multiple modes... Ahem. Isn't that cheating? Isn't move considered two instructions already, a load and store? I guess this is really dependent upon how you define what is and isn't an instruction.

Wrong part number in summary

[mako1138]

It's XC3S1000, not XS3C1000. Been working with these parts too long...

So old it's new.

[LaminatorX]

Sounds a hell of a lot like the read/write head of the Turing Machine to me.

One instruction...

[hey]

... whose first operand is the task to perform. Followed by the necessary operands for that task.

Ummmm

[Sycraft-fu]

"The advantages of RISC are well known -- simplifying the CPU core by reducing the complexity of the instruction set allows faster speeds, more registers, and pipelining to provide the appearance of single-cycle execution."

Is it just me, or does this sound like RISC fanboyism from the 1990s? The "advantages" of RISC are not nearly so clear these days. Indeed, it is getting rather hard to find real RISC chips. While there are chips based on RISC ISA idea (like being load/store and such), they are not RISC. RISC is about having few instructions and instructions that are simple and only do one thing. Those concepts are pretty much thrown out when you start having SIMD units on the chip and such.

These days complex processors are the norm. They have special instructions for special things and that seems to work well. RISC is just not very common, even in systems with a RISC heritage.

I'm just not seeing what this processor is supposed to accomplish, especially being on an FPGA. If you can implement a CPU to do what you need on an FPGA, you can probably implement a dedicated solution on the FPGA that is faster. That is rather the idea of an FPGA over a CPU. You can implement things in hardware that are faster.

"One-der"

[porges]

The hyphen being so everyone doesn't call it "The O-need-er", as in That Thing You Do.

I think it's misleading to call it 1 instruction

[shoor]

There can be different architectures for computers, but, nowadays, for many of us, I'd say there is one particular model of an architecture that is likely to be the only one we're really familiar with, and that automatically comes to mind when one speaks of a computer architecture. It's a rather compartmentalized architecture in which the CPU is the place where opcodes are executed and memory is just a big flat address space for data, including instructions. This "transfer triggered" architecture strikes me as being not so much a 1 instruction computer as one where instructions are implemented in a less compartmentalized fashion, spread out among special units activated by addresses, as opposed to the more plain architecture where bit patterns on the address bus simply activate individual generic memory cells along with a read/write signal. More than that may happen, cache memory comes into play with all it's complications for instance, but the 'model' for the programmer is that simple one.

Re:AAA AA A A

[Anonymous Coward]

Ah, and here's the programmer's manual: clicky [wikia.com]

Pardon me for injecting something serious, but...

[Bruce Perens]

It seems to me that a transfer oriented architecture is conceptually very easy to parallelize.

Re:Pardon me for injecting something serious, but.

[Bruce Perens]

The problem with social networking is that society, as an aggregate, sucks :-)