Intel Allows Release of Full 4004 Chip-Set Details 124
mcpublic writes "When a small team of reverse engineers receives the blessing of a big corporate legal department, it is cause for celebration. For the 38th anniversary of Intel's groundbreaking 4004 microprocessor, the company is allowing us to release new details of their historic MCS-4 chip family announced on November 15, 1971. For the first time, the complete set of schematics and artwork for the 4001 ROM, 4002 RAM, 4003 I/O Expander, and 4004 Microprocessor is available to teachers, students, historians, and other non-commercial users. To their credit, the Intel Corporate Archives gave us access to the original 4004 schematics, along with the 4002, 4003, and 4004 mask proofs, but the rest of the schematics and the elusive 4001 masks were lost until just weeks ago when Lajos Kintli finished reverse-engineering the 4001 ROM from photomicrographs and improving the circuit-extraction software that helped him draw and verify the missing schematics. His interactive software can simulate an ensemble of 400x chips, and even lets you trace a wire or click on a transistor in the chip artwork window and see exactly where it is on the circuit diagram (and vice-versa)."
A great presentation of it all on YouTube (Score:5, Informative)
Link: http://www.youtube.com/watch?v=j00AULJLCNo [youtube.com]
Re:Awesome! (Score:3, Informative)
Re:Awesome! (Score:5, Informative)
For the most part - Newer digital designs are language driven, not schematic driven. The advent of Verilog & VHDL lead to purely digital designs done up in code.
Some of the special devices are done using transistor level design, but synchronous logic these days is a HDL (hardware description language) followed by gate level synthesis, and then autoplace and auto routing.
A lot of fine tuning along the way for high performance items does get tweaked a lot but for the most part, digital chips are created as a coding exercise.
Federico Faggin, intel4004.com (Score:4, Informative)
http://www.intel4004.com/ [intel4004.com] goes into much greater detail about Federico Faggin (primary co-developer and project leader), and the story of his accomplishments before and at Intel, his physical signature on all 4000 series chips, Intel's successful attempt to discredit him and patent his invention (the buried gate) that he invented at Fairchild before coming to Intel, and his departure to found Zilog with some members of his older design team.
Intel has been playing their game their way for a very long time.
Re:If one was produced with a 40nm process... (Score:3, Informative)
Probably the same 740kHz that the original 4004 had.
The manufacturing process used has nothing to do with the maximum clock speed a chip can achieve. It's about energy bleeding (heat loss) and the transistor density. If you manufacture a 4004 using 1950's-era technology, with actual honest-to-goodness 1mm-thick copper wire and large physical transistor switches, it'd be a *lot* bigger, but it'd achieve the same 740kHz that the design allows for.
The reason using a smaller manufacturing process translates into a higher clock speed is that the smaller manufacturing process means that each logic gate takes up a smaller amount of space on the die. This means that you can cram more transistors in to the same area of silicon, allowing you to complete more operations per clock cycle. This way, using a 40nm process instead of the original manufacturing process means that you can build a 4004 that takes up a ridiculously small amount of physical space, not that you can magically build one that's faster than the original design. :)
Re:Awesome! (Score:5, Informative)
> If the Core i7 schematics were released, any old fab company could start making their own i7's for next to nothing.
Wrong.
Let's even imagine for the moment that you really meant that they'd release the verilog/vhdl, instead of schematics. There are still a few minor problems in the way:
1 - Intel really does have absolutely top-notch processing capability. Typically their top-end CPU pushes their top-end process for all it's worth, both in performance and capacity. (I'll add the caveat that "all it's worth" is a moving bar, which is why speed bumps and die shrinks come along as a process and design mature.) Chances are most fabs in the world simply won't be able to handle the Core i7 - not enough transistors.
2 - Let's pretend that you have a fab that can put out bigger-than-postage-stamp sized chips, and they can handle the sheer number of transistors. Most likely you still can't hand over such HDL, push a button, and have a layout come out, even bigger and slower. For one thing, a significant fraction of those transistors are in cache - probably SRAM. HDL doesn't build SRAM, it instantiates it. You need either a compiler or an SRAM design team(s) to get the cache(s) built, and they have to be specifically matched to the interface the HDL is expecting - these aren't garden-variety commodity SRAMs, by any means.
3 - So let's pretend we have SRAMs too, and that the design we had in our back pocket could be tweaked to meet the interface requirements of the Core i7. We have datapath/dataflow problems. In the first place, those datapaths are highly regular - kind of like bit-slices. A lot like bit slices, in fact. Most likely the design was carefully partitioned into functional blocks, and those functional blocks were further partitioned, etc. Then they were floorplanned with an eye to the final design. Far from the smallest concern was getting all of those bits from point-A to point-B to point-C. These things have some pretty big buses inside, and just about everything is high-performance.
In short, a schematic, even verilog/vhdl is a far cry from the whole picture. Even in today's push-button world, you don't push-button a thing like the Core i7, or even latest-generation AMD CPUs, to be fair. You need to have a talented, experienced physical design team, and there's as much work there, maybe more, than simply coming up with the logical design. Then again, frequently the logical and physical design may not be that separated - a really tight feedback loop between the two can work well.
So go back to your super-sized non-optimized chip done with push-button tools - oh and by the way, you may have a hard time finding such tools with enough capacity. The resulting chip won't be a little bigger and a little slower - it'll be a LOT bigger and a LOT slower.
Does anyone know what the technology was for the 4004? (Is that metal-gate, with double-metal, or polysilicon gate with single-poly, single-metal?)