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Tilera To Release 100-Core Processor 191

Posted by timothy
from the and-then-they-stopped-counting dept.
angry tapir writes "Tilera has announced new general-purpose CPUs, including a 100-core chip. The two-year-old startup's Tile-GX series of chips are targeted at servers and appliances that execute Web-related functions such as indexing, Web search and video search. The Gx100 100-core chip will draw close to 55 watts of power at maximum performance."
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Tilera To Release 100-Core Processor

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  • Re:This is great ! (Score:5, Informative)

    by MrMr (219533) on Monday October 26, 2009 @04:42AM (#29870135)
    The 'stock' kernel is ready for 512 cpu's. SGI had a 2048-core single image Linux kernel six years ago.
  • Re:Custom ISA? (Score:3, Informative)

    by EsbenMoseHansen (731150) on Monday October 26, 2009 @04:58AM (#29870195) Homepage

    In general, new instruction sets are mostly interesting in the custom software and the open source software areas. But the latter is quite a large chunk of the server market, so I suppose they could live with that.

    They would need to get support into gcc first, though.

  • Re:Custom ISA? (Score:5, Informative)

    by stiggle (649614) on Monday October 26, 2009 @05:12AM (#29870265)

    From a quick Google - its based on the ARM core (easily licensable cpu core)

  • Re:100? (Score:5, Informative)

    by harry666t (1062422) <[harry666t] [at] [gmail.com]> on Monday October 26, 2009 @05:28AM (#29870327)

    SMP FAQ.

    Q: Does the number of processors in a SMP system need to be a power of two/divisible by two?

    A: No.

    Q: Does the number of processors in a SMP system...

    A: Any number of CPUs/cores that is larger than one will make the system an SMP system*.

    (* except when it's an asymmetrical architecture)

    Q: How do these patterns (power of 2, divisible by 2, etc) of numbers of cores affect performance?

    A: Performance depends on the architecture of the system. You cannot judge by simply looking at the number of cores, just as you can't simply look at MHz.

  • Re:Custom ISA? (Score:5, Informative)

    by ForeverFaithless (894809) on Monday October 26, 2009 @05:51AM (#29870447) Homepage
    Wikipedia claims [wikipedia.org] it's a MIPS-derived VLIW instruction set.
  • Re:This is great ! (Score:5, Informative)

    by Bert64 (520050) <bertNO@SPAMslashdot.firenzee.com> on Monday October 26, 2009 @06:13AM (#29870535) Homepage

    The information in cpuinfo is only redundant like that on x86/amd64...
    On Sparc or Alpha, you get a single block of text where one of the fields means "number of cpus", example:

    cpu : TI UltraSparc IIi (Sabre)
    fpu : UltraSparc IIi integrated FPU
    prom : OBP 3.10.25 2000/01/17 21:26
    type : sun4u
    ncpus probed : 1
    ncpus active : 1
    D$ parity tl1 : 0
    I$ parity tl1 : 0
    Cpu0Bogo : 880.38
    Cpu0ClkTck : 000000001a3a4eab
    MMU Type : Spitfire

    number of cpus active and number of cpus probed (includes any which are inactive)... a million cpus wouldn't present a problem here.

  • Re:This is great ! (Score:5, Informative)

    by fluch (126140) on Monday October 26, 2009 @06:25AM (#29870557)

    Sources are always appreciated when you tell us something.

    Here is the source: http://www.kernel.org/ [kernel.org]

  • by drspliff (652992) <harry.roberts@NOSPAM.midnight-labs.org> on Monday October 26, 2009 @07:40AM (#29870823)

    The Register [channelregister.co.uk] goes into more detail than this article, as usal.

    The Tile-Gx chips will run the Linux 2.6.26 kernel and add-on components that make it an operating system. Apache, PHP, and MySQL are being ported to the chips, and the programming tools will include the latest GCC compiler set. (Three years ago, Tilera had licensed SGI's MIPS-based C/C++ compilers for the Tile chips, which is why I think Tilera has also licensed some MIPS intellectual property to create its chip design, but the company has not discussed this.)

    So it seems pretty standard and they're using existing open & closed source MIPS toolchains, however there's still "will" and "are being" in that sentence which brings a little unease...

  • Re:Custom ISA? (Score:4, Informative)

    by Narishma (822073) on Monday October 26, 2009 @07:52AM (#29870879)

    Why was this modded Informative? Can we have any links? Because both the article here as well as Wikipedia and an old Ars Technica story claim that it's based on MIPS.

  • Re:What ISA? (Score:3, Informative)

    by Narishma (822073) on Monday October 26, 2009 @07:58AM (#29870917)

    No, they are derived from the MIPS architecture.

  • Yep (Score:5, Informative)

    by Sycraft-fu (314770) on Monday October 26, 2009 @08:14AM (#29870989)

    Unfortunately these days the meaning of supercomputer gets a bit diluted by many people calling clusters "supercomputers". They aren't really. As you noted what makes a supercomputer "super" isn't the number of processors, it is the rest, in particular the interconnects. Were this not the case, you could simply use cheaper clusters.

    So why does it matter? Well, certain kinds of problems can't be solved by a cluster, just as certain ones can. To help understand how that might work, take something more people are familiar with like the difference between a cluster and just a bunch of computers on the Internet.

    Some problems are extremely bandwidth non-intensive. They don't need no inter-node communication, and very little communication with the head node. A good example would be the Mersenne Prime Search, or Distributed.net. The problem is extremely small, the structure of the program is larger than the data itself. All the head node has to do is hand out ranges for clients to work on, and the clients only need to report the results, affirmative or negative. As such, it is something suited to work over the Internet. The nodes can be low bandwidth, they can drop out of communication for periods of time and it all works fine. Running on a cluster would gain you no speed over the same group of computers on modems.

    However the same is not true for video rendering. You have a series of movie files you wish to composite in to a final production, with effects and so on. This sort of work is suited to a cluster. While the nodes can work independent, the work of one node doesn't depend on the others, they do require a lot of communication with the head node. The problem is very large, the video data can be terabytes. The result is also not small. So you can do it on many computers, but the bandwidth needs to be pretty high, with low latency. Gigabit Ethernet is likely what you are looking at. Trying to do it over the Internet, even broadband, would waste more time in data transfer than you'd gain in processing. You need a cluster.

    Ok well supercomputers are the next level of that. What happens when you have a problem where you DO have a lot of inter-node communication? The result of the calculations on one node are influenced by the results on all others. This happens in things like physics simulations. In this case, a cluster can't handle it. You can slam your bandwidth but worse, you have too much latency. You spend all your time waiting on data, and thus computation speed isn't any faster.

    For that, you need a supercomputer. You need something where nodes can directly access the memory of other nodes. It isn't quite as fast as local memory access, but nearly. Basically you want them to play like they are all the same physical system.

    That's what separates a true supercomputer for a big cluster. You can have lots of CPUs and that's wonderful, there are a lot of problems you can solve on that. However that isn't a supercomputer unless the communication between nodes is there.

  • Re:This is great ! (Score:3, Informative)

    by tixxit (1107127) on Monday October 26, 2009 @10:45AM (#29872429)
    Oops, wrong link, Megiddo's paper is here [acm.org].
  • Re:This is great ! (Score:3, Informative)

    by san (6716) on Monday October 26, 2009 @11:45AM (#29873123)

    Take a look at /sys/devices/system/cpu: it has information about cpu topology, cpu hot-swap, cache sizes and layout across cores, current power state, etc.

    It's all there, in an architecture-independent way in /sys/devices.

  • by slew (2918) on Monday October 26, 2009 @04:52PM (#29877203)

    The company [tilera.com] website claims...

      64-bit VLIW processors with 64-bit instruction bundle
      3-deep pipeline with up to 3 instructions per cycle

    I don't know how this could be considered ARM or MIPS-derived...

    A better description might have been in this article [linuxfordevices.com]...

    The Tile64 is based on a proprietary VLIW (very long instruction word) architecture, on which a MIPS-like RISC architecture is implemented in microcode. A hypervisor enables each core to run its own instance of Linux, or alternatively the whole chip can run Tilera's 64-way SMP (symmetrical multiprocessing) Linux implementation.

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