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Intel's Roadmap Includes 4nm Fab in 2022

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  • by SilverHatHacker (1381259) on Monday August 24, 2009 @01:13PM (#29174909)
    The next step of the plan: negative-sized chips by 2050!
  • by captaindomon (870655) on Monday August 24, 2009 @01:15PM (#29174921)
    These are long-term business forecasts for 10+ years down the line. They are thought experiments only, in my opinion. They are still valuable, and something to consider, but still very much a "projection" and not a "concrete plan with funding".
    • by icebike (68054)

      They are still valuable, and something to consider, but still very much a "projection" and not a "concrete plan with funding".

      And you know this HOW?

      Are you privilege to Intel internal budget and development cycles?

      I see no reason this gets your vote for fairy-tale status. The shrinkage from 65nm to to 45nm was achieved about 18 months after the first mass produced 64nm processors hit the market.

      Whether this is actually doable in practice remains to be seen.

      A crystal of bulk silicon has a lattice constant of 0.543 nm, so such transistors are on the order of 100 atoms across in a 64nm chip.

      Cutting that down to 2nm starts to run per

    • by Abreu (173023)

      True that.

      For similar giggles, try reading a Wired magazine from ten years ago...

    • Actually I suspect not. Intel traditionally has been quite cagey about releasing exact specs while being very free for generalised bullshit about morphing materials and the like. If they are saying they will reach 4nm they probably have already figured out either a way to do it, or the method they will use to do it successfully once they've built the materials to do it with, within the time frame. It leaves them a lot of wiggle room later on of course, as you pointed out.
    • by rcamans (252182) on Monday August 24, 2009 @03:10PM (#29176411)

      Actually, I have been privy to Intel planning for many years, as I used to work there. It takes many years to develop the next generation uP. That means that the 16 nm devices are already in initial design stages. Since the overall design process is such a big job, all the supporting hardware is a major part of the design process. Like the fab hardware. So, no, much of this roadmap is not a thought experiment, but already many projects with many members working on the pieces. Otherwise, the plan would never come together when its time has arrived.

    • by uarch (637449)

      True to a degree, though there is definitely money going towards working out the broad details of such a plan.

      While many industries don't create plans that span more than a year or two, the business Intel is in all but requires it. It's absolutely a work in progress and is expected to change over the years but you'd be surprised how accurate these things can be. The broader vision of the Nehalem we see today is not that far removed from the vision of Nehalem they were discussing ~6 years ago.

  • by olsmeister (1488789) on Monday August 24, 2009 @01:20PM (#29174989)
    This is obviously pie-in-the-sky speak from the marketing dweebs, who don't understand the physical limitations that come with a die shrink.
    • by matastas (547484) on Monday August 24, 2009 @01:36PM (#29175213)
      Except for the fact that a lot of the 'marketing dweebs' at tech companies are engineers.

      Just sayin'. Your product management/marketing folks at these firms are often very plugged in to the tech side of things (I should know, being one of them).
    • by MozeeToby (1163751) on Monday August 24, 2009 @01:46PM (#29175371)

      Forget about the limitations of die shrink, what about the limitations of quantum mechanics? I was under the impression that 4 nm is getting awefully close to the point where quantum tunneling makes tansistors unworkable. As in, when you detect a signal, you can't tell if it's there because it should be or because an electron just jumped the gap.

    • They likely have more knowledge surrounding technology for a decade plus roadmap than you do.

    • Re: (Score:3, Informative)

      by 32771 (906153)

      Funny is how everything changes after 2012, they will have a different type of transistors. Maybe the guy really thinks things won't matter after 2012 - nut-case.

      Just in case, I ask you to hold them to their other words too:

      http://www.design-reuse.com/news/4850/intel-building-blocks-10-ghz-processors.html [design-reuse.com]

      Next year we are going to see 10GHz processors, this is going to be an interesting exercise.
      Maybe Tom's Hardware or some other brave soul will manage.

  • by stormguard2099 (1177733) on Monday August 24, 2009 @01:27PM (#29175085)

    "Intel Corp., the largest maker of chips in the world,

    Is it really neccesary to explain who intel is on /.? I think even my parents know that intel makes chips, they put out enough commercials... Are even our taco overlords not really reading TFS before hitting that submit button?

  • ... besides wishful thinking?

    Oh, and given at those dimensions quantum noise (e^KT/q) will be greater in signal strength than a 1 or 0 level I am interested to see just how this works.

    I'd love to see it but for the moment it's just numbers on a slide. About a gazzilion dollars in research are needed to get to those dimensions.

    • Re: (Score:2, Funny)

      by Anonymous Coward

      Well, all you need to do is reduce the value of K...

    • Re: (Score:2, Funny)

      by maxume (22995)

      I'd love to see it but for the moment it's just numbers on a slide. About a gazzilion dollars in research are needed to get to those dimensions.

      I don't pretend to be able to meaningfully comment on how likely they are to make it, but that is a fair description of Intel's business model over the last 30 years.

    • A lot of the troubles that look like fundamental roadblocks (like e^KT/q) become less of an issue at low temperature: quantum tunneling, resistivity, and smallest noticeable voltage change to name a few.

      Let me speculate: say we lived in an era where you could run a medium-thick client with hardware like what we have today, but have a fast Internet link to a datacenter with 4 nm chips designed to work at 20 K or cooler. These chips could use much lower voltages and currents, and could have fewer tunneling p

  • My Roadmap (Score:5, Funny)

    by hippo_of_knowledge (445662) on Monday August 24, 2009 @01:29PM (#29175109)
    It just happens that my personal roadmap for 2022 includes a flying pony that craps gold. I'm cautiously optimistic.
    • Re:My Roadmap (Score:5, Insightful)

      by Locke2005 (849178) on Monday August 24, 2009 @01:43PM (#29175313)
      Give it up. The liability from lawsuits by people who sue after getting hit in the head by heavy gold flying pony crap will bankrupt you, just like it did the owners of the goose that laid golden eggs...
      • The liability from lawsuits by people who sue after getting hit in the head by heavy gold flying pony crap will bankrupt you

        Just pass that liability on to someone else. For instance, you could put it in their employment contract that any damages from law suits will be paid by garnishing the pooper scoopers' wages.

      • by Brigadier (12956)

        for $943.00 for 10oz of pure gold you can buy your own air space.

    • It will be the 20s. You better be wearing a zoot suit when you ride that pony.

    • Well, that is physically feasible. I just have a feeling that you you didn't mean a pony in a ultralight plane, that got his ass stuffed with balls of gold...
      Although you could certainly get someone to sell you that. ;)

  • by SlappyBastard (961143) on Monday August 24, 2009 @01:29PM (#29175121) Homepage
    Even accounting for the successful introduction of new materials for transistors, 12 years to get to 4nm seems a tad ambitious. Also, you have to wonder whether or not they're approaching the top of the S curve.
  • It obvious that by then scientists will have found some of that string they've been theorising about for years and will be using that for interconnects.
    • Re: (Score:3, Funny)

      And I guess wireless networks will be using subspace channels? 802.11s?
      • Already taken: IEEE 802.11s [wikipedia.org].

        IEEE 802.11s defines a mesh-networking protocol which "extends the IEEE 802.11 MAC standard by defining an architecture and protocol that support both broadcast/multicast and unicast delivery using 'radio-aware metrics over self-configuring multi-hop topologies.'"

      • We're in multi-letter territory now. I think the next proposed standard will be called 802.11ac (but it's very early in the process).
    • It obvious that by then scientists will have found some of that string they've been theorising about for years and will be using that for interconnects.

      Scientists will NEVER find the g-string.

    • by Grishnakh (216268)

      Kidding aside, parts of String Theory have already been disproven by some new experiment looking for gravity waves. I believe there was a Slashdot article about it a few days ago.

  • by fuzzyfuzzyfungus (1223518) on Monday August 24, 2009 @01:32PM (#29175165) Journal
    By 2022, the only integrated circuits you'll have will be the ones you carve yourself, with your bare teeth, out of the bones of your children(during those rare times that you aren't fighting off hordes of monstrous rat-men or scavenging for survival in a grim Malthusian dystopia).
    • Re: (Score:3, Insightful)

      by treeves (963993)
      Given the choice between this getting modded funny and getting modded insightful, I guess I'll be thankful it was modded funny.
    • Re: (Score:3, Insightful)

      by Hurricane78 (562437)

      What's to stop you from carving them out of the bone of those rat-men? Are they boneless?
      Or are they actually your children by then? ;)

  • by ishmalius (153450) on Monday August 24, 2009 @01:46PM (#29175365)

    I would suspect that unforeseen developments, such as big advances in 3d circuit design, would alter this schedule a lot. This is simply daydreaming.

    • by TheRaven64 (641858) on Monday August 24, 2009 @01:58PM (#29175519) Journal
      3D chip layouts are part of this roadmap. This kind of roadmap isn't really intended to say what their process will be, however. It's intended to give numbers to their core design teams about how many transistors they will be able to play with, what the latencies will be, and so on. These teams will then start working on designs on the assumption that the predictions are correct, then tweak them a bit if they were wrong. If they go badly wrong, you get something like the Pentium 4.
      • Yeah, if all else fails, Intel can go into the space heater business because their chips can BURN.....
      • 3D chip layouts are part of this roadmap. This kind of roadmap isn't really intended to say what their process will be, however. It's intended to give numbers to their core design teams about how many transistors they will be able to play with, what the latencies will be, and so on.

        I'm unconvinced - the latency characteristics of a 3D architecture are going to be vastly different to those you'll find on any 2D chip, no matter how small you make the features.

        That said, I'm assuming Intel is basing this roadmap on some data with at least _some_ substance, rather than just blindly assuming we can keep pushing Moore's law out forever. I'd be interested to know how much of this is based on existing research and how much is BS.

        If they go badly wrong, you get something like the Pentium 4.

        So I'm going to need a bigger nuclear reactor in my laptop then

  • Power vs Speed (Score:4, Interesting)

    by Efreet (246368) on Monday August 24, 2009 @02:09PM (#29175657)

    It seems to me that rather than the identity and timeframe for the different technology nodes (which anyone who knows Moore's law could have given in advance) the interesting thing from that slide is what it says about delay scaling and energy scaling. Whenever you shrink your process you have a certain amount of gain that can go into either making the chip faster or making the chip more power efficient. For a long time back in the day people wanted to stay at 5 volts to preserve compatibility, so everyone just kept putting it into going faster. Nowadays chipmakers try to go for a more balanced strategy.

    But here, on this chart, Intel is saying that they're going to a delay scaling of "~1", staying at pretty much the same speed. And they're looking to increase their energy scaling from "~.5" to ">.5". So it looks like we really have topped out in terms of GHz.

    • Gigahertz hasn't been relevant since the Pentium 4 days. Now that Intel is focusing on more performance per clock, comparing Ghz is only useful if you are comparing two chips within the same line. Anything else and it's apples and gorillas (it's just that different!) Or would you rather have a 1.4 Ghz Pentium III over a 1.2 Ghz CULV Core 2 Solo?
    • For a long time back in the day people wanted to stay at 5 volts to preserve compatibility, so everyone just kept putting it into going faster.

      I don't think preserving compatibility had much to do with concentrating on making things go faster. If you wanted to make a low voltage chip that was compatible with 5v power and TTL data then that would be fairly trivial (onboard voltage regulator and some TTL switching at the edges). The simple fact is that for a long time there was pretty much no need for trying to make things consume less power - no one cared about power consumption. Eventually we got to a point where we *had* to care about power co

  • I don't really pay too much attention to the chip business, so I'm wondering how well, historically, Intel has followed their roadmaps? Are they like an actual roadmap of a, uh, road, that you can follow, or more like a "Roadmap to Peace" that's made because it looks good and people expect you to, even though everyone knows it's not going to work out?

    Anyone got a roadmap from 1996 or so, so one can see how well it was followed?

  • of course intel showed "plans" for this. they have investors who don't understand the limits of miniaturization to snow.

  • by pseudorand (603231) on Monday August 24, 2009 @02:32PM (#29175965)

    That's great. Planning for the future must truly be what separates man from beast. I do the same thing. Here's my personal roadmap:

    2010) - Get in shape, including 6-pack, benchpressing twice my weight and being able to do a Triathlon in Olympic-qualifying time.
    2011) - Win Powerball. Quit job
    2012) - Use lottery winnings to build self-sufficient compound to survive Mayan apocalypse.
    2013) - Now that I'm the only one in the world with means of survival, all the girls will like me. Procreate wildly to start new human race.

    • Re: (Score:3, Funny)

      by SilverEyes (822768)
      Hmm... 2013 can't be great for the gene pool. I guess it may be balanced out as 1/2 of the first generation's genes come from such an ambitious person.

      Or maybe

      2014) Run out of lottery money on alimony payments :P
  • by Animats (122034) on Monday August 24, 2009 @02:59PM (#29176267) Homepage

    There have been formal semiconductor roadmaps to the future since 1992. There's an consensus roadmap [itrs.net] updated annually by an industry group.

    This isn't a blue-sky thing. It tells all the players what they need to do to keep up their part of the technology. The fab-equipment people, the device physics people, the etching people, the mask people, the substrate people, the design tools people, etc. all have to push their parts forward. The roadmap tells them how far each piece has to be pushed.

    These roadmaps are available for past years, and you can see how the industry has tracked the roadmap. It's reasonably close for any five year period. The big change in the last decade is that heat dissipation is starting to dominate the problem. The roadmap now focuses on memory devices, which have low activity per cell compared to compute elements and aren't yet power-limited.

    The current consensus is that the improvements to known technology can get down to 22nm, and then it gets hard. The roadmap assumes CMOS transistors; other devices are discussed, but aren't factored into the mainline predictions.

  • integration capacity of chips will increase much higher compared to fabrication process

    In other words: "we can imagine much more than we can actually produce in this physical reality".

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