Prototype Motherboard Clusters Self-Coordinating Modules 115
An anonymous reader writes "A group of hardware hackers has created a motherboard prototype that uses separate modules, each of which has its own processor, memory and storage. Each square cell in this design serves as a mini-motherboard and network node; the cells can allocate power and decide to accept or reject incoming transmissions and programs independently. Together, they form a networked cluster with significantly greater power than the individual modules. The design, called the Illuminato X Machina, is vastly different from the separate processor, memory and storage components that govern computers today."
I.... I... (Score:0, Insightful)
don't understand.
Re:So? (Score:2, Insightful)
Re:Transputers, anyone? (Score:5, Insightful)
Re:What's the bus on this? (Score:3, Insightful)
I'd guess from the 14-pin connectors and the fact most smaller ARM microcontrollers can't do parallel data transfers under DMA they're using the SPI bus which may run at 72Mbps. Of course that would also mean the bus either needs to be shared for every device or operated in a token ring style with the associated propagation delays. I'd guess the latter because you'd be pushing to get 72MHz SPI data across a large number of devices due to the capacitance it would introduce to the transmission line.
All in all sounds like an interesting academic excercise but of no real-world importance. I expect they'll find all their power and cost savings will be eaten up by requiring hundreds of devices to compete with a single piece of silicon. A better commercial solution would be to put lots of ARM cores on single chips (or FPGAs for development) but then it would make sense to use a better bus arrangement so that would largely invalidate anything they develop.
Mainframe (Score:3, Insightful)
So it's a small, shitty mainframe.
Re:Transputers, anyone? (Score:3, Insightful)
shit design (Score:1, Insightful)
as one poster had said, it would be much more sensible to integrate multiple cores onto an FPGA, and put the real time into the implementation of a bus that could realistically move data between the cores
not to mention that their choice of parts was sub-optimal. the cortex m3 is not the suggested replacement for arm7 by accident, it offers 1.25 dmips/mhz (compared to this arm's 0.89 dmips/mhz), an instruction set with optimized code density versus performance, more predictable interrupt handling, mpu, probably better power consumption, etc. for practically the same price.
if you ask me this is an academia project run by a bunch of hippies who are spending their time on all of the wrong aspects in this kind of decentralized computing concept.
Redundancy (Score:2, Insightful)
Can they make the cluster survive a destruction of several nodes?
There are many situations where this would be beneficial such as space craft design and military electronics. Even with several nodes severely damaged, the machine can re-route processing to the remaining nodes. Although overall processing speed might be reduced, there will be no loss of functionality.