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IBM and AMD Create First 22nm SRAM Cell 83

Posted by kdawson
from the moore-and-moore-tiny dept.
arcticstoat notes an announcement from IBM that, along with technology partners, they have produced the first working sample of a SRAM cell built on a 22nm fabrication process. According to the article, this represents the next generation after 32nm process chips and won't be in products for some years. "The technology was developed with several partners, including AMD, Toshiba, STMicroelectronics and Freescale, as well as the College of Nanoscale Science and Engineering, where IBM performs a lot of its semiconductor research. IBM says that the cell's development involved 'novel fabrication processes,' including high-NA immersion lithography..., high-K metal gate stacks, extremely thin silicide, damascene copper contacts, and advanced activation techniques."
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IBM and AMD Create First 22nm SRAM Cell

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  • When will it stop? (Score:5, Interesting)

    by 4D6963 (933028) on Tuesday August 19, 2008 @05:04PM (#24664473)
    22 nm?? Aren't we dramatically approaching the theoretical limit? What is the theoretical limit by the way?
  • by TheMeuge (645043) on Tuesday August 19, 2008 @05:12PM (#24664557)

    Well, a single silicon atom has a radius of 110pm. I assume silicon dioxide molecule is ~500pm, which is something like 40X smaller than the 22nm process.

    However, silicone dioxide is not perfectly stable and can "leak", as far as I understand it, which limits the process somewhat.

    Again, assuming you need something 100X larger area-wise, you're looking at maybe a factor of 4X remaining until the process can't be shrunk any further.

    But I am not an engineer.

  • by x2A (858210) on Tuesday August 19, 2008 @06:07PM (#24665267)

    I think the limits we're hitting at the moment are not so much due to the material we're cutting into, but the light we're using to do so. To cut finer we need narrower wavelength (=higher energy) light. We're already hitting the very high end of the ultra-violet spectrum (around 10nm) and approaching x-ray light. As the wavelength decreases, all sorts of other things start to change. Materials the used to reflect the light now start letting photons through, lenses no longer have any effect etc, so new ways have to be found to control light at higher frequencies.

    But even here there are ideas to get around the problems, such as using quantum effects like creating interference patterns (I believe I read recently, but don't quote me on it) to cut details finer than the wavelength of the light.

  • by iris-n (1276146) on Tuesday August 19, 2008 @07:14PM (#24666061)

    This "quantum stuff" you talk about is probably tunnelling, which will make electrons leak the transistors if they are too small.

    The exact distance is hard to tell, but in my STM I use around 10 angstroms (fuck ASCII), to get a sizeable current through a potential wall. So, I bet that 20 angstroms would suffice to make it negligible, and so, accounting for other instabilities, I would agree with parent in 5 nm.

  • Re:IBM and AMD (Score:4, Interesting)

    by Bender_ (179208) on Tuesday August 19, 2008 @07:22PM (#24666133) Journal

    Almost...

    Silicides are used to create low resistivity contacts to doped silicon. Typically a metal is deposited on the wafer surface and then heated to react with the crystalline substrate to form the silicide. Commonly used silicides are NiSi, CoSi and TiSi.

    You got the copper right. The here appears to be that they are using copper down to the silicon substrate. Copper does easily "poison" the electrically active regions and is hence typically only used in higher level wiring layers. Getting it down to the silicon is challenging.

    The advanced activation techniques refer to thermal processing steps that are used to incorporporate N and P dopants into the crystal lattice. The challenge here is to heat the wafer to above 1000C within seconds. IBM is probably a laser or flash lamp process for this.

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