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IBM AMD Hardware

IBM and AMD Create First 22nm SRAM Cell 83

Posted by kdawson
from the moore-and-moore-tiny dept.
arcticstoat notes an announcement from IBM that, along with technology partners, they have produced the first working sample of a SRAM cell built on a 22nm fabrication process. According to the article, this represents the next generation after 32nm process chips and won't be in products for some years. "The technology was developed with several partners, including AMD, Toshiba, STMicroelectronics and Freescale, as well as the College of Nanoscale Science and Engineering, where IBM performs a lot of its semiconductor research. IBM says that the cell's development involved 'novel fabrication processes,' including high-NA immersion lithography..., high-K metal gate stacks, extremely thin silicide, damascene copper contacts, and advanced activation techniques."
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IBM and AMD Create First 22nm SRAM Cell

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  • by Anonymous Coward on Tuesday August 19, 2008 @05:13PM (#24664563)

    New manufacturing processes are typically tested by producing SRAM cells, because they're a relatively typical structure and big arrays of SRAM cells are easily tested to measure the defect rate.

  • by wizardforce (1005805) on Tuesday August 19, 2008 @05:20PM (#24664689) Journal

    Aren't we dramatically approaching the theoretical limit?

    yes.

    What is the theoretical limit by the way?

    for Silicon it's probably around 10nm or so. as for what is thought to be possible, molecule size components measuring a few nm.

  • This is amazing! (Score:1, Informative)

    by Anonymous Coward on Tuesday August 19, 2008 @05:29PM (#24664777)

    IBM says that the cell's development involves.. high-NA immersion lithography, high-K metal gate stacks, extremely thin silicide, damascene copper contacts, and advanced activation techniques."

    Wow! That's how my shampoo works too!

    I wonder if the SRAM tingles too...?

  • by cyfer2000 (548592) on Tuesday August 19, 2008 @05:32PM (#24664831) Journal
    22nm could be the limit of bulk planar CMOS device, next step maybe 16nm finFET. See this [solid-state.com] for more information.
  • Re:IBM and AMD (Score:4, Informative)

    by Anonymous Coward on Tuesday August 19, 2008 @05:46PM (#24665023)

    In other news IBM and AMD have used words I don't know

    Is that what you meant to say?

    Silicide [wikipedia.org]. Damascene [wikipedia.org]. And have you never heard of a Damascene conversion?

  • by blind biker (1066130) on Tuesday August 19, 2008 @06:12PM (#24665311) Journal

    I don't mean to be offensive, but almost all those numbers are just pulled from your ass (and I am sure you'll agree).

    For the record, today exist technologies for depositing atomic monolayers of various oxides and even elements. Also, if you think of it, CNTs are nothing more than graphene cylinders - therefore, a carbon atom monolayer.

    Furthermore, CMOS transistors with 17nm long gates have been fabricated already in the distant 2006. Planar CMOS with gates of 15nm have been fabricated in "prehistoric" 2001! And if you think that is impressive, check out this article from the even more distant past [aip.org]

    So, 22nm is far from a physical limit, which is a statement easily demonstrated - by historical events, so to say.

  • Re:IBM and AMD (Score:5, Informative)

    by vigour (846429) on Tuesday August 19, 2008 @06:21PM (#24665387)

    In other news IBM and AMD have hired linguists to invent new words for this process. "silicide, damascene copper contacts, and advanced activation techniques." seemed far to cool to saddle with the brand- name of the new "Blubberon(TM)" and "Humpderon(TM) processor line.

    You need to think before mouthing off in ignorance.

    Silicides are silicon based compounds, eg Copper Silicide, Cu_5 S. The high purity of the Si used by IBM etc means that the formation of Silicides in their samples is unlikely to come from impurities in the wafers (Fe, Co, Ni and other transition metals are generally the worst offenders). So they are most likely to form at Si-stack interfaces after annealing (essentially baking) their samples (chips).

    Damascene copper is contacts are small interconnects made in multi-step stages.
    1.There's a lithography step (patterning & chemical wet-etch) to make trenches for the copper connects.
    2.Followed by either electrochemical deposition, or sputtering of the copper.
    3.Finally after an etch/polishing step you have your connects.

    "advanced activation techniques" refers to modifying the surface of the silicon wafer, and/or deposited layers on the silicon to increase deposition rate, and current efficiency. In the case of electrodeposition, you need to aim for a current efficiency of more than 10% (as in, for a given applied potential, measured current/charge, how much metal has been deposited compared to what you would expect). An electrochemist working in industry would be able to give a much more accurate value than this.

    It's all a lot more complicated than this, and optimising each step is a painstaking process, and yes IAAPBOWIMSNSP (I am a physicist, but one working in magnetic systems not semiconductor physics), but that is the general gist of it.

  • by warrior (15708) on Wednesday August 20, 2008 @02:01AM (#24669271) Homepage

    They're also usually made from _the_ smallest transistors on the die for density reasons. Aside from being able to print these features you also need to reliably set the threshold voltages of all the transistors to make a cell that is both writeable and read-stable. This is not easy to do. For the FET sizes involved in this cell you're probably looking at only tens of dopant atoms setting the Vt. It only takes a few more or a few less dopants to really shift the Vt of said device which could push it into a point where you either can't write the SRAM cell or it flips when you try to read it. Once a process is reliably yielding good SRAMs it's usually "ready to go".

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