Tilera Releases 64-Way Chip Dev Tools

eldavojohn writes to tell us that Tilera has released a Linux-based development kit for their 64-core system on a chip. "The Tile64 is based on a proprietary VLIW (very long instruction word) architecture, on which a MIPS-like RISC architecture is implemented in microcode. A hypervisor enables each core to run its own instance of Linux, or alternatively the whole chip can run Tilera's 64-way SMP (symmetrical multiprocessing) Linux implementation. An 'iMesh' switching interconnect, developed by Tilera's founder, MIT professor and serial entrepreneur Dr. Anant Agarwal, is said to eliminate the centralized bus intersection that limited scalability in previous multicore designs."

Licensing containment barrier??

[sweet_petunias_full_]

I went on to read their in-depth article (linked to the main article) at http://linuxdevices.com/news/NS8981295285.html [linuxdevices.com] and I found this:

"Another touted benefit is the ability to consolidate control- and data-plane functions on a single device, with "solid-wall" processor boundaries reinforcing security and licensing containment barrier. In this regard, the Tile64 chip resembles another heavily multicore MIPS64 chip, Cavium's 16-way Octeon."

Does anyone know what the heck a "licensing containment barrier" is? It definitely sounds like a performance hit if it's turned on. And if it's forced to have it on then this design just lost a lot of its sex-appeal.