Low Voltage Is Key To Energy-Efficient Chip 127
An anonymous reader writes in with news from the International Solid State Circuits Conference in San Francisco of a new energy-efficient chip designed by researchers at MIT. It's said to be able to run on 1/10 the power of current chips. Texas Instruments worked with MIT on the design, which is maybe five years from production. "The key to the chip's improved energy efficiency lies in making it work at a reduced voltage level, according to... a member of the chip design project team. Most of the mobile processors today operate at about 1 volt. The requirement for MIT's new design, however, drops to 0.3 volts."
Physics (Score:1, Interesting)
Comment removed (Score:3, Interesting)
Re:How can that work? (Score:3, Interesting)
Pretty much everyone who uses them for fun
This has already been done before (Score:2, Interesting)
Re:All well and good (Score:3, Interesting)
True enough, there's certainly a different degree of "like" between dynamic and static in that respect.
I admit I am an analog person and my digital design classes were a long time ago (in internet years). Sorry if my information is out of date.
Well a long time ago in Internet years might put that right around the time of the Alpha? It was one chip that I know made heavy use of dynamic logic in order to reach such high frequencies before others did. It seemed to fall out of favor mostly for complexity and manufacturability reasons. And what is compared to that the minor problem that it makes silicon debug harder when you can't down-clock the chip too much because then the dynamic logic stops working.
I also think these small super low power chips are far and away more interesting, and more important to our future lifestyles, than speed demon behemoths.
That's clearly where everything is headed. It is an interesting design problem for sure, but in my heart I like making chips that go fast.
Leakage Power! (Score:2, Interesting)
1. Dropping Vdd to a CMOS transistors requires you to drop the threshold voltage to maintain performance.
2. As the two voltages approach each other, theres an increase in the current in the substrate (the current which flows between n-wells in a typical CMOS transistor).
3. This substrate current ends up contributing to massive amounts of leakage current.
I couldnt resist - the handy eq. from my VLSI Design for Deep submicron book says something along the lines of
Isubstrate =u0*cox*(w/l)*Vt^2 *e^((Vgs-Vth )/n*Vt)
u0 : carrier mobility
Cox: gate oxide cap
w&l: transistor dimensions
Vt : thermal voltage
n : some tech parameter
Vgs: Voltage between Gate and Source
Vth: Threshold Voltage
Re:Wow! (Score:2, Interesting)
A few thoughts (Score:1, Interesting)
Let's assume they when with adjusting the threshold voltage. In order to make a low threshold voltage possible and practical, you'd have to be able to set the threshold voltage very precisely over process and temperature, etc, or else you'd get a zero or negative threshold voltage, resulting in an depletion-mode transistor (google it) that was always on, which wouldn't exactly be good for power consumption.
On a different note, it seems they use an integrated DC-DC converter to adjust the transistor supply voltage seen by the transistors on the fly. DC-DC conversion reduces the efficiency of a circuit, but 90%+ efficient switching converters are available, and for an ninefold increase in efficiency, that would be worth it. Unfortunately, switching regulators are also noisy. The little spikes caused by a buck or buck-boost converter could conceivably cause some of the transistors to unpredictably flip, especially if they're operating at such a low supply voltage.
Apparently they've solved all these issues, if it made it to ISSCC. ISSCC is the big leagues of circuit - they don't let snake oil or unproven claims in.
Re:How can that work? (Score:3, Interesting)
It's also a property of the doping levels of the silicon. Basically, you need to bring a certain amount of charge under the channel to turn the device on. This depends on the substrate material, but also depends on how much charge is available (i.e. doping).
In a given process, you can different flavors of transistors, each with its own threshold voltage. In a 90nm process I'm currently designing in, the digital devices have a threshold of about 250mV. Of course, I'm an analog designer, so that just make my work harder. :) We would normally design with 0.6V threshold devices. The digital devices are faster, but the analog devices have much more gain. But you can't design with higher threshold devices below about 2V. We're at 1.5V, so we need the lower threshold devices.