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Hardware Technology

Low Voltage Is Key To Energy-Efficient Chip 127

Posted by kdawson
from the breaking-the-barrier dept.
An anonymous reader writes in with news from the International Solid State Circuits Conference in San Francisco of a new energy-efficient chip designed by researchers at MIT. It's said to be able to run on 1/10 the power of current chips. Texas Instruments worked with MIT on the design, which is maybe five years from production. "The key to the chip's improved energy efficiency lies in making it work at a reduced voltage level, according to... a member of the chip design project team. Most of the mobile processors today operate at about 1 volt. The requirement for MIT's new design, however, drops to 0.3 volts."
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Low Voltage Is Key To Energy-Efficient Chip

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  • Physics (Score:1, Interesting)

    by Anonymous Coward on Tuesday February 05, 2008 @07:30PM (#22314646)
    Hmm. P=V^2/R, so dropping the voltage from 1 to 0.3 drops the power by a factor of (1/0.3)^2 ~ 10. How many MIT researchers did that take?
  • Process Counts (Score:3, Interesting)

    by Colourspace (563895) on Tuesday February 05, 2008 @07:59PM (#22314986)
    It's very simplistic to say that with voltage drops comes power efficiency - process geometry and materials play a part here too (and I'm not even going to mention the issues with noise tolerance and problems with SSO - Simultaneous Switching Outputs at the 0.3v level). So called 'current' (90nm) geoms are a nightmare for power leakage due to the the relatively small atom thickness that goes to make the gate of the switching transistors. You need to look at such tricks as gate oxides and other power mitigating technologies... BTW - When I say 90nm is current, I know people are doing 65nm, 45nm, 32nm and beyond (which are, given process geometry/power efficiency/newer techniques slightly better in some ways) but the lower geoms are slightly ahead of the curve somewhat..
  • by Chemisor (97276) on Tuesday February 05, 2008 @08:02PM (#22315028)
    > who the hell still uses BJT's?!?!?!?!?

    Pretty much everyone who uses them for fun :) You can get 2N3904s for 3c each, so it doesn't bother me if I accidentally let the smoke out of one. FETs are much more expensive, are easy to fry if you aren't extra careful to ground before touching, and are present in far fewer circuits you can find online. Then there's the fact that my old Horowitz and Hill only has one chapter on them and so I am just not as familiar with their properties. Eventually, when I'm a "God of circuit design", I'll probably use lots of FETs too, just like the big guys...
  • by trajan96 (901853) on Tuesday February 05, 2008 @08:26PM (#22315348)
    There have been 150-200mV microcontrollers (pdf) at the University of Michigan for some time now: http://wimserc.org/research_highlights/Submiminal_Processor_Research_Highlight.pdf [wimserc.org] Conference paper 3: http://vlsida.eecs.umich.edu/resource.php?grp=1 [umich.edu] what is new is TI and MIT are involved in a commercial low voltage product. But thats still 5 years out. MIT is good at getting press.
  • Re:All well and good (Score:3, Interesting)

    by Chris Burke (6130) on Tuesday February 05, 2008 @09:04PM (#22315800) Homepage
    Everything 'likes' super-threshold, the question is will they work.

    True enough, there's certainly a different degree of "like" between dynamic and static in that respect.

    I admit I am an analog person and my digital design classes were a long time ago (in internet years). Sorry if my information is out of date.

    Well a long time ago in Internet years might put that right around the time of the Alpha? It was one chip that I know made heavy use of dynamic logic in order to reach such high frequencies before others did. It seemed to fall out of favor mostly for complexity and manufacturability reasons. And what is compared to that the minor problem that it makes silicon debug harder when you can't down-clock the chip too much because then the dynamic logic stops working. :P

    I also think these small super low power chips are far and away more interesting, and more important to our future lifestyles, than speed demon behemoths.

    That's clearly where everything is headed. It is an interesting design problem for sure, but in my heart I like making chips that go fast. :)
  • Leakage Power! (Score:2, Interesting)

    by borowcm (1233996) on Wednesday February 06, 2008 @12:18AM (#22317182)
    From what I can remember from my Low Power VLSI class...

    1. Dropping Vdd to a CMOS transistors requires you to drop the threshold voltage to maintain performance.
    2. As the two voltages approach each other, theres an increase in the current in the substrate (the current which flows between n-wells in a typical CMOS transistor).
    3. This substrate current ends up contributing to massive amounts of leakage current.

    I couldnt resist - the handy eq. from my VLSI Design for Deep submicron book says something along the lines of
    Isubstrate =u0*cox*(w/l)*Vt^2 *e^((Vgs-Vth )/n*Vt)
    u0 : carrier mobility
    Cox: gate oxide cap
    w&l: transistor dimensions
    Vt : thermal voltage
    n : some tech parameter
    Vgs: Voltage between Gate and Source
    Vth: Threshold Voltage

  • Re:Wow! (Score:2, Interesting)

    by Spy Hunter (317220) on Wednesday February 06, 2008 @01:26AM (#22317604) Journal
    Actually, I seem to recall reading about a guy who had proven that there was no theoretical lower bound on the amount of energy it would take to do a given computation (assuming the computation was 'reversible' [wikipedia.org]). Contrast this to an electric motor, where the desired result is mechanical power output, so obviously at least as much electrical energy must go in as mechanical energy comes out. When the desired output is merely 'computation', there may be no lower bound on the energy input required.
  • A few thoughts (Score:1, Interesting)

    by Anonymous Coward on Wednesday February 06, 2008 @02:39AM (#22317994)
    I'd have to read the paper to know for sure, but I'd think they'd have to do some fundamental device process work to make a chip work at that low of a supply voltage. The threshold voltage (or "turn-on voltage" as some people call it) of a transistor doesn't scale with reducing device size, although there are steps that can be taken to adjust the threshold voltage in process, like ion implantation of various types. It's either that or they're operating it in subthreshold. The only problem with subthreshold operation is that it's incredibly slow. I guess it's conceivable though, for low-power, low-intensity applications where speed isn't a factor.

    Let's assume they when with adjusting the threshold voltage. In order to make a low threshold voltage possible and practical, you'd have to be able to set the threshold voltage very precisely over process and temperature, etc, or else you'd get a zero or negative threshold voltage, resulting in an depletion-mode transistor (google it) that was always on, which wouldn't exactly be good for power consumption.

    On a different note, it seems they use an integrated DC-DC converter to adjust the transistor supply voltage seen by the transistors on the fly. DC-DC conversion reduces the efficiency of a circuit, but 90%+ efficient switching converters are available, and for an ninefold increase in efficiency, that would be worth it. Unfortunately, switching regulators are also noisy. The little spikes caused by a buck or buck-boost converter could conceivably cause some of the transistors to unpredictably flip, especially if they're operating at such a low supply voltage.

    Apparently they've solved all these issues, if it made it to ISSCC. ISSCC is the big leagues of circuit - they don't let snake oil or unproven claims in.
  • by Komi (89040) on Wednesday February 06, 2008 @11:35AM (#22321398) Homepage
    The activation voltage of a transistor is variable- it's a property of the materials its made of. .7 is a common one and thus used in a lot of texts, but it isn't set in stone.

    It's also a property of the doping levels of the silicon. Basically, you need to bring a certain amount of charge under the channel to turn the device on. This depends on the substrate material, but also depends on how much charge is available (i.e. doping).

    In a given process, you can different flavors of transistors, each with its own threshold voltage. In a 90nm process I'm currently designing in, the digital devices have a threshold of about 250mV. Of course, I'm an analog designer, so that just make my work harder. :) We would normally design with 0.6V threshold devices. The digital devices are faster, but the analog devices have much more gain. But you can't design with higher threshold devices below about 2V. We're at 1.5V, so we need the lower threshold devices.

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