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AMD Hardware

AMD Multi-Core G3MX DRAM Interface Details Emerge 43

Posted by ScuttleMonkey from the new-toys-all-the-time dept.
MojoKid writes "New details have emerged regarding AMD's upcoming G3MX technology. The 'future Opteron Platform' AMD mentioned in their press release seems to be built around a CPU currently codenamed 'Hydra'. Hydra will still feature an on-die memory controller, but unlike current platforms it will be geared for DDR3 memory. The processor will interface to one or more G3MX chips, which in turn provides the interface to the memory slots. G3MX will act as a memory port extender for the memory controller in the CPU socket and a serial link to the RAM.The electrical signaling between the memory controller and G3MX is based on HyperTransport 3.0."
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AMD Multi-Core G3MX DRAM Interface Details Emerge More

AMD Multi-Core G3MX DRAM Interface Details Emerge

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  • DDR3? (Score:2, Funny)

    by Anonymous Coward
    I didn't even know there was a DDR2. But then again, I'm not a dancing japanophile idiot.

    • Re: (Score:2, Funny)

      by moderatorrater ( 1095745 )
      They're up to 4 or so on the arcade game (not counting the "turbo" editions, etc). Regarding the RAM, DDR3's been around for a while iirc.

  • So a mini north bridge chip? (Score:5, Insightful)

    by Brit_in_the_USA ( 936704 ) on Wednesday August 22, 2007 @05:05PM (#20322721)
    Looks like a mini northbridge - just memory and no PCIe or AGP or anything else.

    I wonder what the latency hit is going to be with lots of them on a server and moving data from one branch of a tree to another?
    BR> I guess if they don't deviate from HT3 spec too much lots of other applications could emerge for this chip, with the inclusion of partnerships to bring DSP's and other accelerators / CPU alternatives to the server line this is turning more and more into Lego.
    • I don't really see any way the latency hit could be worse than (or even as bad as) the hit Intel took from FB-DIMMS. AMD wouldn't be hyping this if it had the same Achilles' Heel that Intel's solution has.

    • Re: (Score:2)

      by hyc ( 241590 )
      No more than the latency hit for a multi-socket system today when one CPU needs to access memory residing on the other CPU's memory controller. That's the beauty of HyperTransport.

      Of course I asked AMD for this 2 and a half years ago. Nice to see it's finally come to life.
      http://forums.amd.com/forum/messageview.cfm?catid= 28&threadid=34279 [amd.com]
      They didn't need to wait for HT 3.0 to release this, it would have worked perfectly well back then.

  • Marketing Translation (Score:2, Funny)

    by Anonymous Coward
    Translation: "We've taken some moderately new technology and repackaged it with buzz words to make you think you need it."

  • good luck AMD (Score:2, Interesting)

    by edxwelch ( 600979 )
    It'll be interesting to see if AMD actually get to deliver this technology before they run out of money (http://uk.theinquirer.net/?article=41700)

  • Actually... (Score:5, Informative)

    by Brane2 ( 608748 ) on Wednesday August 22, 2007 @05:59PM (#20323255)
    this concept seems quite sensible.

    They are using G3MX chips as a sort of multiplexer and connecting it to the CPU though a couple of lanes with high-speed signaling.

    Internal logic within HYDRA CPU will have the capability to use either conventional onboard memory controller and drive the DDR-3 RAM directly or when socketed within board with G3MX extenders, use that same lines for communication through the G3MX.

    Since the load on the lines will be much smaller and constant and since all lines are unidirectional, each line will be capable of much higher signaling speed, so they will be able to use 4x as much RAM as before per CPU node.

    If that is not enough, several Hydra CPUs could be connected through HT links- just like now with existing Opterons.

    CPU-G3MX connection is much more direct and probably need not to use extra cycles for node addressing, unlike conventional internode communications through HT links, so time overhead could be considerably smaller...

    Also, compared to FB-DIMMs, when accessing to some RAM bank here user only pays some throughput penalty (if any), but doesn't suffer much extra latency- with FB-DIMMs data hos between the modules and each hop costs one clock, so access time for 4-th module is longer than to the first one in a group.

    Not to mention that GMX-3 chip could host some L3 cache if needed in some later implementation and that combined speed of all G3MX chips is probably greater than existing solution, so interesting effects could be achieved with meory interlieve.

    It could very well be that such combination could have distinct speed advantage even in many workstation applications...

    • They are using G3MX chips as a sort of multiplexer and connecting it to the CPU though a couple of lanes with high-speed signaling.

      So it's the RDRAM architechture in reverse?

    • Re: (Score:3, Interesting)

      by raxx7 ( 205260 )
      Intel, IBM et all have been using similar memory extenders on server chipsets for quite some time.
      For example, check the XMBs on Intel's E8500 chipset.

      The reason why Intel has moved from such memory extenders and pushing FB-DIMM is simple though: there won't be a 4th DIMM on G3MX. DDR3 isn't likely to support more than 2 registered DIMMS per channel, 4 rank each.

      • Re: (Score:2)

        by Brane2 ( 608748 )
        But with FB-DIMM you get to pay high latency penalty with higher number of modules that really it doesn't matter if in theory you can do it, in practicall world latencies will kill you.

        Besides that, on Optys you can always add one extra CPU with its set of 4x G3FX chips and corresponding RAM.

        Sure, latencies through extra HT link will be higher, but you get extra CPU that you can useif you want to, and however you cut it, with extra memory you have to pay some extra latencies.

        All things considered, this so

        • Re: (Score:3, Insightful)

          by raxx7 ( 205260 )
          No, it's not all bad. GM3X is a sensible solution, with a different set of tradeoffs than FB-DIMM.

          In both FB-DIMM and G3MX case you have the basic concept: Memory Controller --- buffer --- DRAM
          The difference is where the buffer is. On G3MX is't on the board and it can handle 1 or 2 DRAM modules. On FB-DIMM it's on the DIMM itself and can only handle one module but buffers can be daisy chained.

          G3MX allows you the flexibility of having up to 2 modules per channel without an extra latency.
          With FB-DIMM, each mo
    • Not to mention that GMX-3 chip could host some L3 cache if needed in some later implementation and that combined speed of all G3MX chips is probably greater than existing solution, so interesting effects could be achieved with meory interlieve.

      Surely you must mean L4. Barcelona has L3 on die. :)

      C//

      • Re: (Score:2)

        by Brane2 ( 608748 )
        But G3MX is meant for Barcelona successors AIU, and those need not necessarily have L3.

        Even if so, L4 wouldn't hurt, especially if it is much larger than smallish L3 on first Barcelonas.

        Also, if there would be separate channel for peripheral DMA access, internode G3MX communication and on-chip SIMD units, extra cache could nicely decouple CPU from RAM most of the time, especially with maybe one or two extra instructions for software L4 cache prefetch...

        • But G3MX is meant for Barcelona successors AIU, and those need not necessarily have L3.

          Well, perhaps, although I thought there was this big virtualization argument in favor of common L3 and dedicated L2 caches.

          What I'm interested in is what total b/w their are targeting to a single piece of silicon. I recall that Niagara2's got 50GB/s. Woodcrest is doing 21GB/s or so. Those N2's must be something else again for throughput-oriented computing.

          C//
  • Is it just me or does this product seem to be an alternative to using expensive DIMMS using normal grade DDR3 memory rather than using expensive FB-DIMMS like intel does on their enterprise hardware and also increasing the amount of slots per system since you have a more ideal fanout with the memory split up like its shown in article?

  • "Based On" Hypertransport 3.0? (Score:3, Interesting)

    by Courageous ( 228506 ) on Thursday August 23, 2007 @12:30AM (#20326437)
    Something bugs me about the chart in TFA.

    It shows 13 lanes outgoing and 20 lanes incoming to each G3MX unit.

    And then it references hypertransport. However, hypertransport is a duplex standard. It can transfer data 20GB/sec in each direction per 32bit link.

    So how am I to interpret this.

    Anyway, supposing that each of those 3GMX units is anything at all similar to an 32-lane HT3.0 protocol, we're talking 80GB/sec of memory bandwidth per processor. That's just nuckin' futz! :-)

    C//

    • Re: (Score:3, Insightful)

      by Brane2 ( 608748 )
      They have probably meant to say that the same pin drivers will be used as they are on the HT-3.0 links.

      Given that it took a considerable effort to develop such superfast drivers on silicon chip and that it is now in their existing know-how it seems only reasonable to leverage it to the maximum use...
  • The Real Question is how much less time will my renders take compared to not having a G34X! chip?

  • I gave up (Score:1, Troll)

    by tacocat ( 527354 )

    I used to be a huge fan of the AMD CPU architecture. Clearly a better, faster, more product compared to Intel

    But over the years there has been so much splitting and fragmentation of the architectures from both companies and I hardly know what I'm getting anymore. Too many cute names and not enough information about what they are really doing. It would have been a lot better for both companies if they just made three lines of CPU and left it at that

    Of course, my choice for the simplified structure would

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