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AMD Hardware

A Three-Way AMD Opteron Server 137

Abdul tips a thin little review up at The Inquirer of the Themis Slice. "The Slice is a three socket Opteron machine with two PCIe slots and two Infiniband 4x ports... Why would you want three sockets rather than four? Easy, latency. Any CPU in a 3S system is one hop away from any other CPU. In a 4S system, you can be two hops away. This adds latency, and more importantly, you take a big hit on cache coherency latency. This kills performance."
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A Three-Way AMD Opteron Server

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  • CoProcessors? (Score:5, Interesting)

    by tji ( 74570 ) on Monday August 13, 2007 @02:57PM (#20215197)
    Wasn't AMD also talking about licenses or agreements with other companies to allow for different types of coprocessor chips to be used alongside their processors?

    There is some interesting potential in that realm.. Crypto accelerators for VPN, SAN, or other devices. Multimedia encode/decode accelerators (encode 1080P H.264 in real time?). Inevitable video game acceleration devices (physics co-processor, accelerated NIC chip, 3D GPU offload processor?).

    Those would be even more interesting in home-user oriented Athlon64 boards. Multi-socket opteron boards are out of my price range.
  • Where's the specs? (Score:2, Interesting)

    by achbed ( 97139 ) * <sd&achbed,org> on Monday August 13, 2007 @03:06PM (#20215297) Homepage Journal
    There's no reference to this board/blade anywhere on the manufacturer's site. The only thing I can find is that this guy saw this board at a conference and took a shot and wrote a really short article about it. Ok, so a 3-way is a bit of a novelty, but good luck getting it to work. Isn't most microcode on the processors designed with 1, 2, or 4 way in mind? And isn't the cache coherency microcode embedded (at least in part) on the processors themselves? So setting up a 3-way using current processors would actually increase latency and error-checking, correct? IANAPD, but this seems like a dead end.
  • by Laxator2 ( 973549 ) on Monday August 13, 2007 @03:09PM (#20215331)
    The article states that with 3 processors one gets better performance, latency wise, because in a triangle configuration any processor cache is just one hop away. You can have 4 processors in a tetrahedron configuration and still have any processor one hop away. Of course it will take 3 hypertransport connections per processor just for the internal communications, so a 4th connection is needed for at least one processor to connect to the northbridge. The quad-core Opteron will have a maximum of 4 hypertransport connections, is that right ?
  • Re:Weird (Score:2, Interesting)

    by poopdeville ( 841677 ) on Monday August 13, 2007 @03:29PM (#20215559)
    I was under the impression that this latency issue was caused by the fact that there is no positive solution to the utility problem [wolfram.com]. Essentially, each core is connected directly to the other two, in a planar graph. There's no way to connect each of 4 cores to the other three without the connections intersecting, at least if the connections are made on anything topologicically the same as a convex subset of the plane (that is, no planar graph exists).

    This can be solved directly by creating chips with multiple planes on which connections can be made, or indirectly by running messages through other cores, at the cost of latency. Then again, I have no idea if multi-layer chips are in production.
  • Re:Weird (Score:3, Interesting)

    by pla ( 258480 ) on Monday August 13, 2007 @03:31PM (#20215571) Journal
    If it is impossible, please explain why.

    Problem 1)
    Draw four circles on a piece of paper.
    Now draw a line from every circle to every other circle without crossing any lines.

    Problem 2)
    Draw four circles on a piece of paper. Draw two "pins" on each.
    Now draw a minimal path between any two circles such that you can only start and stop at a pin, and only one connection can go to a single pin.



    You have the right idea for problem 1, that for low-N, you can just route connections through different layers of the board. But that only works for low-N and doesn't generalize (though in fairness, neither does to the "3-CPU" solution).

    For problem #2, no real solution exists other than limiting the degree of connectedness to some low number of pins (2 gives the simplest case above single-CPU, a daisy-chain or ring topology), or having centralized signal switching (star topology).
  • Multi core (Score:3, Interesting)

    by jshriverWVU ( 810740 ) on Monday August 13, 2007 @03:41PM (#20215711)
    Curious if it can take multi-core cpu's. Having a 3way system with dual core opteron's sounds really nice.
  • Re:IBM System x3755 (Score:3, Interesting)

    by mr_mischief ( 456295 ) on Monday August 13, 2007 @04:39PM (#20216481) Journal
    Actually, I've never worked for IBM, and I keep pricing eComStation. I'd kind of like to use that on a system or two. Warp 3 is getting a bit paunchy. I don't want to drop it, though, because then I'd be down to Linux, BSD, Windows, OS X, DOS, and AmigaOS.

    Visopsys, ReactOS, OpenSolaris, plan9, Minix, QNX, MMURTL, OpenVMS, Haiku, and some others could serve for utility and novelty in varying degrees, but I already have plenty of software for OS/2.

    Yes, I'm an avid system collector. If you have hardware or software that's old, obsolete, and quirky, I probably want it.

Understanding is always the understanding of a smaller problem in relation to a bigger problem. -- P.D. Ouspensky

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