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AMD Hardware

AMD Releases Image of Phenom/Barcelona Die 129

MojoKid writes "A few weeks ago, AMD released information on new branding for their desktop derivatives of the Barcelona core, now dubbed the Phenom FX, X4 and X2. If you're unfamiliar with Phenom, the processors will be based on AMD's K10 architecture. They've been tight lipped about specifics, but we know that it will feature a faster on-die memory controller, support 64-bit and 128-bit SSE operations, and they'll be outfitted with 2MB of on-chip L2 cache (512KB dedicated per core) in addition to 2MB of shared L3 cache. This week, instead of revealing some more of the juicy details regarding those enhancements, AMD just sent over a tasty photo of a Phenom die. At least it's something."
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AMD Releases Image of Phenom/Barcelona Die

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  • Re:and socket type? (Score:5, Informative)

    by Josef Meixner ( 1020161 ) on Saturday June 02, 2007 @06:42AM (#19362039) Homepage

    In every press release [amd.com] AMD stated it will run in AM2 sockets. If I remember correctly it will not be able to use the new hypertransport links, support for the new power saving functions (it can switch off complete cores if they aren't needed) in AM2 sockets, it will need AM2+ for that. Sorry, I am far too lazy to search for a reference for those last bits of information, it is something I read in a magazine (paper version).

  • Re:a mobile version? (Score:5, Informative)

    by Eukariote ( 881204 ) on Saturday June 02, 2007 @07:04AM (#19362097)

    For mobile, AMD has gone a different route for now, they have reworked the K8 for extremely low power: http://www.theinquirer.net/default.aspx?article=39 894 [theinquirer.net]. The two cores and memory controller get independent voltage planes. And the cores can clock up and down independently. It makes good sense: for mobile, low power is crucial.

    Many of the high-end features (double FPU units, hypertransport interconnects, and so on) of the Barcelona design are not required for a laptop, and add power draw caused by static leakage, even when not in use. In due time, though, AMD will no doubt rework the K10/Barcelona core into a mobile design. Probably they will release a moderately power mobile Barcelona version before that, for high-end workstation type laptops.

  • by TheRaven64 ( 641858 ) on Saturday June 02, 2007 @08:11AM (#19362323) Journal
    The number of cores per die is limited by two things:
    1. Number of transistors per die.
    2. Number of transistors per core.
    Sun can put more cores on a die by having fewer transistors per core, it's as simple as that. Sun is bucking industry trends quite heavily at the moment (see here [informit.com]) by reducing the amount of die space take up by cache. Intel are right at the opposite extreme, with well over 50% of the Itanium die taken up with cache. Modern x86 chips are sitting at around the 50% mark. Intel could easily make a quad core chip with no cache for the same price as their dual-core chips, but performance would be much worse. They could make a single core chip with 50% more cache for the same price, but, again, performance would be worse.

    Exactly what the best trade-off is depends on your workload. Sun are aiming at the web-app server market. It's a good business decision, since this is a rapidly growing area. It's also one of the easiest workloads to run, since it's inherently massively parallel; each web-app typically has a few tens to a few thousand users per server. If one thread in a T1 has a cache miss, then there are a huge number of others that are able to take advantage of the processing resources. Intel and AMD have to support a lot of legacy single-threaded code. A cache miss in one of these is expensive. Main memory accesses are of the order of 100-200 cycles, and so a cache miss every 100 cycles would cause a 50% performance reduction. For the T1, with its 8 contexts per core, it would cause a negligible performance reduction overall, as long as the other threads still have work to do.

  • by Wdomburg ( 141264 ) on Saturday June 02, 2007 @10:30AM (#19362953)
    Sun put eight in-order single-issue integer only cores on a single die. AMD is putting eight full superscalar cores with branch prediction, virtualization extensions, vector units, blah, blah, etc, etc. Very different design philosophies producing chips with very different aims.

    Sun's foray into more traditional processor designs - the Rock - isn't expected to ship until 2008 and will feature only four cores.

    The only designs actually on the market with eight traditional cores would be the IBM POWER4 and POWER5 lines, but those are dual core dies in a multi-chip module, reminiscent of the Intel scheme.
  • Re:Hype it up (Score:5, Informative)

    by ChrisMaple ( 607946 ) on Saturday June 02, 2007 @03:17PM (#19365021)
    The only reason that AMD is still alive is that Intel made a series of blunders. Intel went exclusively with the expensive RAMBUS technology, kept the northbridge off-chip, chose clock speed over processing power. During the same period AMD integrated the memory controller, developed hypertransport, and emphasized processing power over clock speed. As a result, for several years AMD maintained a small performance advantage and slowly gained market share. Because Intel maintains a superior process technology, AMD's advantage was only a small one. Intel is much larger and can afford the huge expenses invloved in keeping the process advantage.

    Now that Intel is mostly past its blunders, it still has the advantage of superior process and is likely to maintain that advantage. Unless AMD can pull more rabbits out of its hat, its goose is cooked. I want AMD to regain the performance lead, but I don't think it's going to happen.

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