New Server Chip Niagara

* * Beatles-Beatles writes "Sun recently announced their latest release in server technology. The UltraSparc T1 processor, code-named Niagara, has eight computing engines on a single chip, with each core capable of handling up to four tasks at once." With this new processor Sun hopes to get a leg up on the competition. The Niagra chip is being billed as an "eco-friendly" chip because of its low power requirements. From the article: " [...] removing the world's Web servers and replacing them with half the number of UltraSparc T1-based systems would have the same effect on carbon dioxide emissions as planting 1 million trees."

Better link

[Anonymous Coward]

Better link here [sun.com].

Comparisons to the cell?

[Anonymous Coward]

These processors are a step in a different direction. Like the cell processor, they lack features like branch prediction, have small, very simple pipelines, etc. However, that isn't really all that bad, esp. on some tasks where your CPU is mostly just idling waiting for IO to finish anyway. I wonder if these "simple but gets the job done" CPUs will see an even wider market in the future. As the article said, they are cheaper and consume less power than their competitors

Re:Apple need this

[Anonymous Coward]

low power requirements != low enough for a laptop.

Niagra = 70 watts
G4 = 19 watts

Re:What about I/O?

[SQL Error]

Specs here [sun.com]. Four 144-bit DDR2-533 interfaces. That's more memory bandwidth than a quad-Opteron system.

The lowdown

[gtoomey]

http://www.sun.com/processors/UltraSPARC-T1/specs. xml [sun.com]

Since the story is devoid of content:
- up to 8 cores, 4 threads per core
- integrated RSA
- 3MB L2 cache
- 90nm process
- 1.2 GHz

Re:Comparisons to the cell?

[Quicksilver]

Not really the same thing at all. The cell uses one master to control several specialized units. Niagara is just what is sounds like. 8 cores on 1 piece of silicon. They all are the same and the all can run any Sparc code.... unlike the Cell which isn't compatible with anything and each unit can only work on what it is specialized in.

Re:What about I/O?

[the eric conspiracy]

The 4 threads per core is designed exactly for that issue. If a thread is waiting for memory, execution can proceed on a different thread.

Re:nasty stuff

[Anonymous Coward]

Your comparison of the types and amounts of arsenic and the acids used in photolithography is disingenuous at best. Go into any chip-fab plant and look at the cyanide emergency kits on the wall to get some idea of what they deal with in reality. I worked with people who did chip-fab in another part of our lab and one of them died from a phosgene leak. Acids they use include hydrocyanic acid (cyanide poisoning) and a variety of heavy metals for doping.

By the why, the green discoloration on potatoes that grow exposed to the sun is chlorophyll and solanine with small amounts of arsenic. You'd get a tummy ache from eating a green potato as opposed to the amounts used in chip-fab.

Re:Massively multi-core x86s

[tomstdenis]

Dude, a PPC 440 is 6mm^2 and consumes 700mW of power at 667Mhz. You could easily fit a dozen on a die the size of a P4 and still take FAR less than this Niagra core. At a rated 1200MIPS per core a die with eight of them would net you close to 9600MIPS max. Of course you'd need some form of L2 cache and high speed internal bus.

Similar the new ARM cores Cortex [arm.com] it takes roughly the same power at 1Ghz which gives it apparently 2000MIPS. The area is about the same as PPC 440. So in theory you could hook 4-8 of these up as well and get a killer chip too..

Point is Suns quotes of being "2 possibly 3 generations ahead" is totally bullshit. They're at most one generation ahead. It takes one multi-core ARM or PPC to totally destroy this.

Tom

Arbor Day Foundation

[jbeaupre]

If you're willing to do the planting, the National Arbor Day Foundation will send you 10 trees for $10. http://www.arborday.org/shopping/Memberships/membe rships.cfm [arborday.org] Get 10% of the registered users on Slashdot to sign up for this (and plant them) and you're close to a million.

Re:nasty stuff

[InvalidError]

"Sparc's strength in the early Internet days was always throughput - even under load"

Are you implying that you can have useful throughput under no load? How do you measure this idle throughput advantage?

The Intel/AMD architectures are historically single-threaded desktop-centric where the most important thing usually is to run one thing really fast. Sun, however, was always in the HPC/workstation game where overall throughput matters most, latencies and single-thread performance be damned. These two groups were playing pretty different games up to recently.

But now, Intel/AMD have hit a GHz and complexity brick wall. They are forced to promote multi-threading multi-core at the desktop-level and optimize their future desktop chip designs for multi-threaded application throughput rather than single-threaded performance. Imagine what would happen if AMD and Intel could afford to quit competing on single-threaded performance overnight: goodbye complex deep out-of-order execution, goodbye branch-prediction and speculative execution - those transistors would be much better spent on implementing quad-threading cores to keep every pipeline filled with useful instructions that will retire cleanly on every clock.

Sacrificing single-thread performance for simultaneous multi-threaded throughput in the above-described way has been the name of Sun's game for the last few years.

Obsession with single-threaded performance is what costs current x86 CPUs the most power. Of course, in the P4/HT case, there is the added power and transistor costs of trying to be a jack-of-all-trades who predictably turned out as a master-of-none. (The P4's uOP replay engine is a neat idea... but re-executing the same stupid uOPs until they meet retirement conditions is woefully wasteful, whoever designed and bothered to patent this should be fired.)

Re:What about I/O?

[Paul Jakma]

The whole point of Niagara is to get higher throughput *despite* memory latencies.

Re:Or even easier....

[nelsonal]

Please mod this up, recycling paper has zero impact on cutting of forests, paper pulp "trees" are grown on farms.

Re:Massively multi-core x86s

[tomstdenis]

Law of diminishing returns?

Compare a 2MB L2 cache on a P4 to a box with 1MB of L2 or 512K ... the cache ends up contributing less and less to the overall performance.

What is also important is associativity. If you have a low-assoc cache, meaning a given address has few places in the cache it could reside you end up wasting more space. That's why [iirc] the AMD processors have high associvity L2 caches. They make good use of the 512K available.

At my previous job we built Gentoo distros on 128 and 256K semprons and the time to build wasn't really that different even though we were building 100s of packages.

So you could have a relatively high performance web server or file store [or whatever] without the 2MB of cache stuck on the back of the thing.

Tom