Anyone Using JHDL for Programmable Logic?

gte910h asks: "I am an embedded developer who is learning how to program programmable logic devices (CPLD's and FPGA's). I have looked at VHDL and other Hardware Description Languages, but they seem so obtuse compared to C or Java. Has anyone tried any of the tools based off of general purpose programming languages, like JHDL. Do they work as well as VHDL and other HDL's? These would make things this type of development acessable to more people if they work well enough." Are packages similar to JHDL available for other languages?

Celoxica DK1

[Anonymous Coward]

is a C-based HDL. We've been reviewing it, and its pretty impressive. Not really C, but fairly similar. One of our engineers managed to port a complete GSM codec (originally in C for some 16 bit DSP) from scratch in about 3 weeks, so its easy to use. Check out their site [celoxica.com].

Some thoughts from a JHDL developer

[omnirealm]

I worked in the BYU Configurable Computer Lab (the lab that developed JHDL) for about a year and a half. I built the JHDLOutput and the Design Rule Checker (DRC) components of the system.

One semester, the EE department decided to use JHDL as the HDL for the logic design class (then it was EE320), and I was the teaching assistant that "specialized" in the actual tool (JHDL). Basically, JHDL was used as an introductory HDL for the students. The results were interesting.

In short, most of the class succeeded in building an LC2 processor entirely in JHDL, interfacing it with memory, and programming it (netlist, run through Xilinx backend tools, transfer bitstream) onto a Spartan chip. Most of the issues arose in the students struggling with object-oriented programming (creating a "Wire object" and a "2:1 Multiplexor object") and in the subtle details of how to interface circuit components with one another. A lot of students would get sections of their circuits ripped out by the Xilinx tools for failing to simply attach one component to another. The schematic viewer, waveform viewer, and other debugging tools proved effective in helping with the actual design.

Automated and dynamic simulation is easily performed in the simulator GUI and in testbenches. There is a Finite State Machine generator. There is parameratizable Floating Point arithmetic unit (its size depends on the number of wires you pass to it when you instantiate it; there are many more modules like this). Parameters can be assigned to the circuits in JHDL to, for example, instruct the Xilinx tools how to assign pins to top-level wires. Multiclock functionality exists. My DRC subsystem can dynamically instantiate circuits and run user-specified (and user-defined) checks on those circuits through a GUI. JHDL is fairly sophisticated, and it is an impressive tool given that it is mostly a student-developed application.

Before I left the lab (I had a very heavy classload), we were kicking around the idea of making JHDL Open Source. There are many legal issues we had to deal with... I'm not sure how it's looking now.

Clarification

[gte910h]

I asked about JHDL because it is based off Java. I wasn't aware that Verilog was based off C, or I might have looked there (C is my first choice in Programming Languages when given the option). The JHDL people claim that people learn it much faster than VHDL, so I was asking you guys for verification of its applicability and ease of use. I would like to actually get something working, which is a lot easier in something halfway familiar to me than something completely alien. English is much closer to German than it is to Chinese, and similarly that much easier to learn

A tutorial on Verilog [cmu.edu] is made available from a CMU professor. I think that Verilog will be more than sufficiently C-like to ease me into the PLD world.

I am aware of the huge difference of what kinds of behavior you are programming when you are using programmable logic devices vs. microcontrollers. But just because I am looking at a different paradigm doesn't mean it wouldn't be nice if some of my skills would transfer. I want to gain proficiency in PLD's because of the fact they can implement functionality otherwise requiring complex circuits. This is useful and I can't currently use it in my designs without another engineer to do the PLD.

I was really curious about the accessibility of the language. Java-like syntax would make it easier to entice more people to try to learn this skill, as Java is familiar to many people in the environments in which I work. I would bet Verilog has gained many adopters b/c of its similarity to C, who would otherwise use schematic entry to program PLD's, or avoid the parts altogether

To function well in the climate and level of embedded development today, you have to be able to do both sides of the equation if you want to be at all independent. I have seen horrific program design choices by people formally trained in EE, and I have seen atrocious, laughable circuits from those formally trained in CS.

A software guy sees a fault in a product and says it is a hardware problem.A hardware guy sees a fault in a product and says it is a software problem. The real engineer fixes the damn problem and tells the other two to grow up and pull their heads' out of their asses.

Re:HDL 'programming'

[jcorgan]

The 'conceptual model' that is embodied in high-level languages such as C/Java or Verilog/VHDL couldn't be more different:

• With C and Java, a developer is presented with an abstract "machine" that has one or more "flows of execution". The developer creates a sequence of data/variable manipulations and flow control constructs which guide execution based on the results of logical tests. This is a view of the world as a "stream of instructions."
• With Verilog and VHDL, the developer is "sequencing" a "state machine" (with or without a synchronizing clock) by routing massively parallel binary state between logic elements that update that state. This is a view of the world as a "lot of things happening at once, connected by the rules that govern them."

It's not surprising that people (such as the poster of this story and the students you mention) have trouble shifting between them.

Re:Celoxica DK1

[Anonymous Coward]

I've used DK1 for a number of large scale FPGA projects.

In terms of productivity and time to market, JHDL/VHDL/Verilog/SystemC are dead in the water.

RISC CPU in JHDL

[Jan]

In June '01, Mike Butts published an independent reimplementation of the xr16 instruction set architecture, written in JHDL.

See:
http://www.easystreet.com/~mbutts/xr16vx_jhdl.ht ml
http://www.fpgacpu.org/log/jul01.html#010731
http://groups.yahoo.com/group/fpga-cpu/message/4 88

Thoughts From A Professional FPGA Developer

[Light's Shadow]

I worked in the Virginia Tech Configurable Computing Lab for many years. I hold a Ph.D. in electrical engineering from VT. Currently, I work for Annapolis Micro Systems, Inc. http://www.annapmicro.com, the world's leading FPGA-based computing solution provider. I have developed several small applications using JHDL that were used as case studies in my dissertation. I've developed large scale high-performance applications using VHDL as part of my job. I have also used a tool that, I helped pioneer, called CoreFire(tm). I can offer the following point of view about the merits of the various options.

First, VHDL was developed as a simulation language. Later, when industry discovered that what it really wanted was an automated tool that converted an HDL to a hardware design, VHDL was adopted as an input language for that process. Large portions of the VHDL language cannot, in fact, be used when the goal is to synthesize the resulting code into hardware. So, hardware development with VHDL is actually done with a subset of VHDL, typically referred to as synthesizable VHDL.

VHDL does indeed provide a higher-level approach to developing hardware. Some relatively simple language constructs can lead to a complex hardware implementation. It is, for instance, very easy to describe a state machine in VHDL and have the synthesis tool translate that state machine into gates and flip flops.

Since VHDL was not designed as a synthesis language, the translation of a VHDL construct into a hardware construct is not well defined. Each company that markets a VHDL synthesis tools approaches the problem differently. So, a given construct synthesized by one tool might lead to a well-optimized piece of hardware, while it leads to an ugly mess when synthesized by a different tool. To get reliable results, engineers that use synthesis tools must become experts in the particular synthesis tool they use.

Another disadvantage of VHDL is that it is very difficult to produce reusable code. It provides some mechanisms that seem useful for this purpose at first, but which, with experience, turn out to fall short. As a professional FPGA application developer, I've abandoned VHDL. I typically spend much too much time fighting with the language or the synthesis translation process.

So, what to use if not VHDL? The first thing that needs to be understood about JHDL is that it does not allow you to write your application in Java and then synthesize it into hardware. JHDL provides a mechanism for doing structural hardware design. So, you're not, for instance, writing a while loop in Java and having that translated into gates. What you would have to do is describe, in terms of the interconnection of the available hardware primitives and macros, the detailed hardware structure of your while loop. JHDL does not raise the accessibility of FPGA design. You still need to be a hardware engineer. You still need to understand the low-level nature of the hardware that you're building. What JHDL does is make it easier to do those things. JDHL is a Java-based library that allows you to build hardware structures using a real computing language.

Re:Easy to write vs easy to debug

[kiatoa]

Try verilog in conjunction with a rule based formal verification language for bug free code instead of using a draconian approach like VHDL to enforce correctness.

VHDL has so much overhead and is cumbersome to write in in my opinion. Verilog also seems to generally simulate faster. Also the free (GPLed) icarus verilog simulator is better than any free VHDL simulator I've been able to find :).

Also when it comes to writing behavoural testbenches I could never live without fork/join.

Lastly many of the deficiencies in verilog have been corrected in the Verilog 2000 spec.