Tilera Releases 64-Way Chip Dev Tools

eldavojohn writes to tell us that Tilera has released a Linux-based development kit for their 64-core system on a chip. "The Tile64 is based on a proprietary VLIW (very long instruction word) architecture, on which a MIPS-like RISC architecture is implemented in microcode. A hypervisor enables each core to run its own instance of Linux, or alternatively the whole chip can run Tilera's 64-way SMP (symmetrical multiprocessing) Linux implementation. An 'iMesh' switching interconnect, developed by Tilera's founder, MIT professor and serial entrepreneur Dr. Anant Agarwal, is said to eliminate the centralized bus intersection that limited scalability in previous multicore designs."

Oblig.

Imagine a beow... oh, never mind....

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Actually you might want to imagine a Beowulf cluster of them. You'd more likely run MOSIX or OpenMOSIX on the chip to handle the migration from logical machine to logical machine on the same chip, but you can't then use that to build a cluster as you'd get

Released?

I thought the chip has been out for a few months; I feel bad for anyone who has been trying to use the processor with no development tools.

Also, it looks like the tools have been released to Tilera's customers, not to the public. A shame, since I'm sure a

Licensing containment barrier??

I went on to read their in-depth article (linked to the main article) at http://linuxdevices.com/news/NS8981295285.html [linuxdevices.com] and I found this:

"Another touted benefit is the ability to consolidate control- and data-plane functions on a single device, with "solid

Re:Licensing containment barrier??

> It definitely sounds like a performance hit if it's turned on.

No, if anything they pitch it as a performance gain.

The idea is to run Linux (or OS of your choice), with various control plane functions (it can have an IP address, you can do config, stats collection etc etc), on say (making up these numbers!) 4 of the cores, while the other 60 cores are running without an OS (they offer a BIOS like environment with basic functions to get access to the backplane and subsequently the packets) doing data-plane functions, perhaps doing deep-packet inspection for QoS delivery, security functions (IPS?) etc.

The Linux side, particularly the kernel isn't going to contain your real IP, while the data-plane side is all your secret-sauce. It involves embedded style programming without lots of OS support, but you get speed and the networking vendors are used to this sort of model - it sure beats the hell outa doing it in an ASIC on the dataplane side which is what they're used to.

This isn't an attack on open source - it's using it in a sensible fashion IMO. However, for the paranoid types who've seen the fud, they probably pitch this split of operations as a "licensing containment barrier" cause a marketing person thought it might help somewhere.

--Q

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It's like an antimatter containment field - circular and serves the purpose of being dramatic on television.

Jargon overload!

Can anyone please translate this to Layman? I mean I do know bits and pieces about computing but this is really unintelligible for anyone but maybe hardware engineers.

Simple version.

They have set up an 8x8 grid of processors, not unlike a chessboard. Each square on this grid can talk only to adjacent squares (up, down, left, right), with the edge squares connecting to I/O devices. They refer to their network as a mesh, but the correct term for this design is a Manhattan Network. This is not significantly different from a processor I dearly loved in the late 80s, the Transputer. That, too, had 4 connections from each processor, but you were not restricted in how you connected the Transputers together. A grid, it transpired, was not efficient, you needed to arrange the connections to form a hypercube. (Yes, it's 2D, so it's actually a 2D representation of a hypercube. Now stop fussing or I won't get you that Beowulf cluster for Christmas.)

I like the idea, I like the idea a lot, but the fact that they opted for a simple but slow topology doesn't fill me with hope. Especially as they suggest running SMP over it. Processors close to the centre of the "mesh" will be resource-starved. There needs to be strong affinity of a given thread to a given core, where the weighting is by the operations expected and where that weighting can (and will) shift as code blocks change or new threads start. In other words, you want something that is semi-static, semi-dynamic according to need. Only the OS is capable of obtaining that kind of information, so it is the OS that needs to do the dividing, NOT the architecture underneath OR a system administrator.

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I like the idea, I like the idea a lot, but the fact that they opted for a simple but slow topology doesn't fill me with hope.

hypercubes were great in the 80's when everything was multiprocessors and wire lengths didn't kill you. But it turns out that low-dimension networks (ie, a 2d grid) are faster for a network of cores fabbed onto a single processor. while you can decrease

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Very lucid description. The other problem with the design is that you don't get what you expect; using a simple 4-way grid should give predictable latency costs between nodes. Unfortunately their routing algorithm is non-predictable so you can't statically

VLIW

Okay, so I know that VLIW stands for some very long word, but couldn't you have told us what it's an acronym for anyway?

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OK troll. First, you only have to give the source you wrote to people you distribute binaries to. No one else. Of course, they can give them to anyone they want to. Second, you don't have to give the source out to anyone at all IF you don't distribute bina

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Not necessarily. Only if you distribute ALL your binaries with source do you not have to provide source for ANYONE on demand. If you allow written requests for source, you must allow the source to be obtained by ANYONE.

http://www.gnu.org/licenses/gpl-faq [gnu.org]

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Would you like a little FUD with your whine?

In the odd, small, tiny chance that you're not some idiot with an agenda (the wwworld is fast filling up with posts like this), then your lawyers are the ones with an agenda and/or incompetence.

According to your

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Furthermore, after reviewing this GPL our lawyers advised us that any products compiled with GPL'ed tools - such as gcc - would also have to its source code released. This was simply unacceptable.

Now that is an outright lie. Do you realize how many commercial programs were compiled with gcc? The only time you must release your source is if you were linking GPL'd libraries...and at that, the legal issues are still unresolved.

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A quick giggle for "or the Gnu Protective License" barfed up the following:

http://www.news.com/5208-1030_3-0.html?forumID=1&threadID=2246&messageID=11919&start=-1 [news.com]
http://linux.slashdot.org/comments.pl?sid=389856&cid=21705136 [slashdot.org]
http://yro.slashd [slashdot.org]

Look, folks, a real-live alien!

I don't have a hard time believing that this person consults for large companies, because I have met a number of totally clueless people who made big bucks consulting for large companies. That part is quite believable. But really...

(1) If I were a clien

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Clearly some kind of troll.

Note the use of the words:

Recently, ext2, defrag, and.. token ring??

Was that even still around when a student named Linus messaged some newsgroups describing his latest little hobby?

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Was that even still around when a student named Linus messaged some newsgroups describing his latest little hobby?

Well when my brother went to Marist college in 1998, they were still using token ring, so I'd say yes.

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Not mine, but for some peoples routers it's here:
http://openwrt.org/ [openwrt.org] ;D

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Well, I suppose Vista certainly is enough of a strain on hardware to be a fair benchmark.

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Wouldnt you be looking for a development board for it?

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It *is* a dev board. The whole thing is a PCIe riser card, so you can upload firmware from the host machine etc.

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I hear what you're saying - it is sort of annoying.

However, a VC funded startup like this has to be focused. They're going to have a list of customers probably about 10 companies long that they want to sell to, and everyone else at this stage is a distract

You're mixing implementation and architecture

CIISC and RISC describe the architecture. Either can be implemented directly, using horizontal or vertical microcode, or via a translator. RISC is similar to vertical microcode, where each micro-instruction controls part of the core, and VLIW is similar to