AMD Unveils Barcelona Quad-Core Details

mikemuch writes, "At today's Microprocessor Forum, Intel's Ben Sander laid out architecture details of the number-two CPU maker's upcoming quad-core Opterons. The processors will feature sped-up floating-point operations, improvements to IPC, more memory bandwidth, and improved power management. In his analysis on ExtremeTech, Loyd Case considers that the shift isn't as major as Intel's move from NetBurst to Core 2, but AMD claims that its quad core is true quad core, while Intel's is two dual-cores grafted together."

Memory Controllers

[ExploHD (888637)]

the memory controllers now support full 48-bit hardware addressing, which theoretically allows for 256 terabytes of physical memory.
256 terabytes should be enough for anybody.

Re:

[aussie_a (778472)]

No he didn't. But please, don't let that stop you claiming otherwise.

wha?

[macadamia_harold (947445)]

AMD claims that its quad core is true quad core, while Intel's is two dual-cores grafted together.

So Intel's Ben Sander claims that AMD's claim is that Intel claims that their dual-cores grafted together qualify as quad-core technology? That's not confusing at all.

On snap!

[joe_cot (1011355)]

"In his analysis on ExtremeTech, Loyd Case considers that the shift isn't as major as Intel's move from NetBurst to Core 2, but AMD claims that its quad core is true quad core, while Intel's is two dual-cores grafted together."
BUUUUUUUUUURNED
Next week: Intel responds by telling us how fat AMD's mother is.

Once again...

[tygerstripes (832644)]

Firstly, can I just say that stating that "the shift isn't as major as Intel's move from NetBurst to Core 2" is like... er... comparing a decent incremental car improvement with swapping a bicylce for a car. Or something. I'm not saying Core2Duo isn't great tech, but look; Netburst was shit. Everyone knows it. They flogged that horse for far too long, so comparing on the grounds of the proportional improvement is not a useful comment. It's like when the thick kid in school got the "most improved" award, and everyone sat there and went "Well yeah, but what was his alternative?".

As for the quad-core thing, it's the same story all over again. Intel rush out a solder-together-two-chips job to beat the competition to market, and then the actual innovators come out with something coherent that works more efficiently etc.

I'm not saying the AMD will necessarily be better. What I'm saying is I don't care who gets to market 2 months earlier. I want the better chip, and I can live with the mystery for a few weeks.

Although, frankly, I can barely afford to eat having just built a decent Core2Duo rig, so I won't be investing either way just yet...

Re:Once again...

[tygerstripes (832644)]

It wasn't that good. AMD came out with an architecture which, in practical terms, was better designed, while Intel just kept trying to push the envelope with this very hot chip, and steadily lost market share as a result. Core2Duo is fantastic, relatively speaking, but it was a very long time coming...

Re:Once again...

[LaughingCoder (914424)]

Netburst was designed for a market that touted clock speed as the performance measure for CPUs. AMD, with a big helping hand from the gamers, changed the game into rewarding true benchmark/performance rather than simple clock speed. I suppose if Intel had managed to achieve 10GHz clocks their performance would have been top notch, though one wonders how long those instruction pipelines would have to be ... and how much power they would have burned.

Now Intel has out-benchmarked AMD, and is attempting to change the rules again to performance-per-watt. This next wave should be interesting to watch.

Re:

[JebusIsLord (566856)]

Well that's not really completely true though, is it?

I mean, if you read about the K8L architecture, they can throttle the voltage and clock rate for each core independently, and all 4 share a common L3 cache as well. Plus there are additional hypertransport links for inter-core communications.

The Intel solution has none of these, as a direct or indirect result of not being a "true" multicore setup (technologically very similar to a quad-cpu setup, really, let alone two dual core cpus). This doesn't mean th

Note to AMD: We don't care

[cperciva (102828)]

AMD claims that its quad core is true quad core, while Intel's is two dual-cores grafted together

Note to AMD: We don't care about the implementation details. We care about performance, cost, and power consumption; the clock speed, cache sizes, and how cores talk to each other is irrelevant.

For all I care, Intel's "quad core" processor could be using a team of psychic circus midgets.

Re:Note to AMD: We don't care

[by Anonymous Coward]

Some of us do care. Some for work, some for fun. AMD's "designed as quad-core" approach has some notable consequences, especially in the cache layout that (on paper, of course) seems very well suited to virtualization -- much more so than the Intel solution in TFA.

AMD: a shared L3 feeding core-specific L2 caches. Intel: each core-pair sharing a L2 cache. AMD's approach better avoids threads competing for the same data (thanks to copying it from L3 to every L2 that needs it), while keeping access latencies more uniform and predictable (thus better optimizable).

Other AMD enhancements look more like catch-up to Core 2: SSE [and it's "Extensions", dammit, not "Enhancements"] paths from 64bit to 128bit, more advanced memory handling (out-of-order loads versus Intel's disambiguation et al.), more instructions per clock by beefier decoding (more x86 ops through fast path instead of microcode) and more "free" ops (where Intel added way more discrete execution units from Core to Core 2).

If AMD's quad manages to be better due to better memory bandwidth and latency (in practice), then they were quite right about "true quad-core" :)

Re:

[tygerstripes (832644)]

Is that meant to be sarcastic?

You don't care because you don't understand. Performance, cost and power consumption are directly affected by such things as clock-speed, cache, core integration, architecture etc, and different aspects offer different advantages for different uses.

If it were that easy to put a reliable figure on Performance, the Megahurtz shambles would never have happened.

Re:Note to AMD: We don't care

[Visaris (553352)]

Note to AMD: We don't care about the implementation details. We care about performance, cost, and power consumption; the clock speed, cache sizes, and how cores talk to each other is irrelevant.

AMD it taking the route that will give better performance. I hear you saying that soldering some copper pipes with rubber-bands would be fine as long as it would perform. The point is that it will work... just not very well.

If you don't think I'm right, look at Intel's own product roadmap. They plan to release a new version of Kentsfield that has all four cores on one peice of Si, with a shared cache, just like AMD is about to do... only later in 2007 after AMD's version comes out. When the two major chip companies move in the same direction, usually that means it is the right one. The only difference is that AMD is going to get there sooner because they didn't bother to play around with this MCM (Multi-Chip-Module) junk. Intel just wants to get to market first; they don't seem to put quality first.

Re:Note to AMD: We don't care

[aminorex (141494)]

"...what matters is benchmarks..."

Lies, damned lies, and statistics. I both agree and disagree. Throughput on applications is what matters to end users. Synthetic benchmarks are useful (and so matter) in as much as they identify specific architectural performance characteristics for a given implementation. They are less than useful (and do not matter) when they do not correspond in a predictable way to throughput results.

"...vs total power usage..."

For your application, perhaps. Most home and office users don't care about the power dissipation of their CPU, as long as the cooling rig is zero-maintenance. GPUs completely overwhelm small variations in CPU for gamers these days. For high-throughput computing systems, there is a major shared/distributed memory split. For shared memory systems (i.e. capable of scaling throughput on multithreaded applications by increasing CPU counts), interconnect scalability matters more than any thing else, and AMD wins handily. For distributed memory systems, blade farms, etc, scalability and rank density will be determined by power dissipation, and there, finally, I can agree with your comment, and Intel may have a (very small) lead. It's a rather small slice of a diverse market, however.

Amazing analysis

[nanoakron (234907)]

AMD: 4=4
Intel: 4=2x2

Where do they hire these guys?

-Nano.

Hmmmm Wrong.

[Solokron (198043)]

Looks like someone RTFA a bit wrong. Ben Sander works for AMD. He is one of their media presenters. Here are a few of the events he has done: http://www.cpd.iit.edu/cpd/events.htm [iit.edu] http://www.ewh.ieee.org/r4/chicago/foxvalley/meet. thru.mid2005.html [ieee.org] http://www.instat.com/FallMPF/06/conf1.htm [instat.com] http://mtv.ece.ucsb.edu/MTV/index_files/program-mt v.txt [ucsb.edu]

Quad-core vs. dual-dual-core?

[Kopretinka (97408)]

Can anyone please shed some light on the difference (for the user) between a true quad-core and a dual dual-core processor? I expect a quad-core can be cheaper because it is more integrated, but is that it?

Re:Quad-core vs. dual-dual-core?

[Phleg (523632)]

A "true" quad-core means that all of them share the same L2 cache, AFAIK. Basically, performance benefits as they can all use the same high-speed memory cache for L1 misses. This is also extremely useful in the case of multiple processes which aren't bound to a CPU. If process A is scheduled on processor 1, then 2, then 3, then 4, there are going to be a lot of cache misses (since it's in no CPU's L1 cache). With two dual-cores bolted on to each other, processes switching from processors 1-2 to 3-4 are going to incur severe performance penalties as any relevent memory is fetched over the memory bus from RAM.

Re:Quad-core vs. dual-dual-core?

[tomstdenis (446163)]

As others pointed out, inter core communication has to hit the FSB. That makes things like owning/modifying/etc cache lines slower as you have to communicate that outside the chip.

There are also process challenges. Two dies take more space than 4 cores on one die since you have replicated some of the technology [e.g. FSB interface driver for instance]. Space == money therefore it's more costly.

If one dual-core takes 65W [current C2D rating] than two of them will take 130W at least [Intels ratings are not maximums]. AMD plans on fitting their quadcore within the 95W enveloppe. Given that this also includes the memory controller you're saving an additional 20W or so. In theory you could save ~55W going the AMD route.

Also currently, C2D processors have lame power savings, you can only step into one of two modes [at least on the E6300] and it's processor wide. The quad-core from AMD will allow PER-CORE frequency changes [and with more precision than before] meaning that when the thing isn't under full load you can save quite a bit. For instance, the Opteron 885 [dual core 2.6Ghz] is rated for about 32W at idle down from 95W at full load. I imagine the quad-core will have a similar idle rating.

Tom

True QC versus MCM:

[Visaris (553352)]

Intel's QC is really an MCM, or multi-chip-module. That means they have literally grabbed two Conroe (Core 2 Duo) chips off of the assembly line, and mounted them in a single package. From the outside it looks like a single chip, but inside, it has two, separate peices of Si, connected over the FSB. That is the problem: the two chips are connected to the same bus. A single chip presents one electrical load on the bus, and two chips present two loads. This means that the speed of the bus needs to be dropped. That is why kentsfield will have a slower bus speed than normal chips. If you think about it, this is the exact opposite of the situation you want. You have just added a core, so it would be nice to add more bus bandwidth. Instead, the Intel solution lowers the overall bus bandwidth, not to mention that it is a shared bus. The two cores fight each other over a very slow external bus, and this creates a performance bottleneck.

When all four cores are on a single peice of Si, all sharing a L3 cache, the chips don't need to fight over the external bus as much. The cores can share information between them internally, and do not need to touch the slow external bus to perform cache coherency and other synchronization. Also, true QC chip presents one load to the outside bus. This means that the bus speed does not need to drop because of electrical load.

There are many people who don't care how the cores are connected as long as the package works. The point is that the way the cores are connected have a direct impact on performance. We'll be talking about Intel vs. AMD cache hierarchy in 2007 when AMD uses dedicated L2 and shared L3 while Intel uses only shared L2. Expect cache thrashing on Intel's true QC chips with heavily threaded loads when it comes out. Next I'll hear people say that the cahce doesn't matter as long as it works. As long as it works for what? Single-threaded tiny-footprint benchmarks like SuperPi or Prime95? How about a fully threaded and loaded database or any other app that will actually stress more than the execution units?

Re:Intel's Ben Sandler?

[mattmacf (901678)]

Ok guys, CUT THE SHIT!! It's four in the morning and the last thing I want to do is request a new password just to finish posting a comment and come back to find new comments that prompt me to need to go back to my email and login AGAIN

See, some of us just don't ever logout and everytime I come back to my computer Slashdot is waiting happily for me to return. but you couldn't just let that be, could you? nooooooooooo... every JACKASS WITH AN AGENDA and a COMPLETELY UNFUNNY SIG has to dick me around tonight instead of just letting me post in peace.

My apologies, I seriously need some sleep.

--
Forget your password? Have your password mailed to you [slashdot.org] by entering your nickname, uid, or email address.

Re:Socket consideration

[somersault (912633)]

Why - do you think todays processors won't still be useful in 3 years? Most games don't take advantage of current technology for a year or more I'd say, and your office applications/OS are going to run fine on any of today's decently specced systems (3000+, 3Ghz Pentium, doesn't even matter if they only have one core). The only people that can truly make use of multicore chips would be scientists and people who do any other kind of intensive parallel processing, like like graphics rendering. In 3 years you'll probably want a new mobo anyway to take advantage of whatever new-fangled technology has come out. I guess you could say I'm becoming less of a geek these days even though I'm an IT manager, but if my computer works, and plays the games I like sufficiently (say 1280x1024@60fps with details maxed out), I don't see the need for upgrading my processor (I'd upgrade my graphics card before anything else, since graphics cards come out more often and usually would have a larger effect on performance from one generation to the next).

Since most of the chipset is becoming integrated into the processor these days then your argument will make more sense over time, but if you were more patient and waited for things to come down in price, as they always do, and rather quicker than I expect sometimes, then you'd be able to buy a new mobo, ram and processor for the same price as the new processor would have cost 6 months previously (not meant to be a perfect example, I haven't been following the prices of stuff since I built my last system a couple of years ago, but the idea is sound :p )

Re:Socket consideration

[wolrahnaes (632574)]

As the person who responded to your last post explained, that's just not possible with the K8 architecture as it is. The memory controller is on-die and memory technology is evolving, therefore the interface between the processor (where the controller is) and motherboard (where the DIMMs are) must also change.

The closest to a solution we have would be going back to Pentium 2/3 style processor-on-a-card designs which would move the memory slots to an expansion card shared with the processor which would then have a HyperTransport interface to the motherboard.

This works, as some motherboard manufacturers (ASRock on the 939DUAL for one) have implemented something along these lines for AM2 expandability. The problem lies in laying out the circuitry for this new slot, not to mention the incompatibility with many of the large coolers we often use today. It also would become even more complex when faced with another one or two extra HyperTransport lanes as found on Opteron 2xx and 8xx chips, respectively.

AMD made a compromise when they designed K8. On the one hand, the on-die memory controller improves latency by a huge amount and scales much better by completely eliminating the memory and FSB bottlenecks that Intel chips get in a multiprocessor environment. On the other hand, new memory interface = new socket, no way around it.

From what I understand, the upcoming Socket F Opterons will have over 1200 pins in their socket so as to allow both a direct DDR2 interface and FB-DIMM. If I understand FB-DIMM technology correctly, it should end this issue by providing a standard interface to the DIMM which is then translated for whatever type of memory is in use. Logically this will trickle down to the consumers in another generation. For the time being however, AMD has stated that the upcoming "AM3" processors will still work in AM2 motherboards, as they will have both DDR2 and DDR3 controllers.

I guess you won't buy Intel either...

[Visaris (553352)]

I won't buy any AMD processors anymore until AMD clears its socket plans and guaranties a minimum of 3 year availability for processors on a socket.

I suppose that means you won't buy an Intel chip either. Look at what happened with Conroe. Core 2 Duo uses a socket with the same name as the P4 socket, the same number of pins too. But guess what? When Conroe came out there were less than a handful of reasonable boards out of the hundreds of models out, that would actually support it. The voltage requirements changed slightly, the BIOS requirements changed, and the end result was that upgrading to Conroe on a given board was hit or miss. I fail to see how Intel's MB upgrade situation is any better than AMD's. It sounds to me like you're falling for Intel's game: "We kept the socket name and number of pins the same, so that means we have better socket longevity." Sorry, but I'm not falling for it. I've read too many horror stories on the forums from Conroe upgraders that thought they could use their current P4 boards.

Don't get me started on Intel's TDP scam either (AMD's = max, Intel's = average). AMD may not always have the best tech, but I find them to be a much more straight-forward company, with fewer sneaky games designed to trick customers.

And why are we posting a story about AMD's tech said/written by an Intel employee? Sounds like it was biased before it even started to me.

Re:

[masklinn (823351)]

It was indeed, Intel didn't have integrated ("true") dual-core (AMD-style) before the Core architecture. Pentium-D's two cores, for example, had to use the FSB to communicate with one another, they didn't have a specific, fase, core-to-core bus. In the end, they were no better than regular dual-core, except that you only needed a single socket.

Re:

[AcidLacedPenguiN (835552)]

why not make 10 faster?